Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2001-10-26
2004-02-17
Tse, Young T. (Department: 2634)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S371000, C327S144000
Reexamination Certificate
active
06693985
ABSTRACT:
TECHNICAL FIELD
Embodiments of the invention are in the field of processing high-speed digitally encoded analog data.
DESCRIPTION OF THE BACKGROUND
When performing parallel sampling of a serial data stream, clock skew must be compensated for. Clock skew occurs when there is a difference in clock signal timing between the signal being sampled and the sampling circuit. Clock skew can cause the sampling circuit to sample the signal at times during which the received signal does not represent meaningful data. Bit error rate (“BER”) is a measure of transmission errors, typically the number of erroneous data bits over the total number of bits transmitted. In most systems, there is a maximum BER that cannot be tolerated.
In serially transmitted binary data, one way to extract original data is to sample more bits during one bit period. This technique is called oversampling. From oversampled data, the receiver can extract the best samples with minimum error, due to nearby data and clock information. Oversampling includes sampling multiple times in a period of time during which the received signal is expected to represent meaningful data. The multiple samples collected, however, include bad samples and good samples, and the bad samples must be discarded. In some prior circuits that perform oversampling, the received signal frequency is too high for a single sampling circuit to perform the required number of sampling operations per time period. Therefore, several parallel sampling circuits are used. Each of the sampling circuits is “fired” by a clock signal with a distinct point in time, so the sampling circuits are fired in sequence. For example, an oversampling ratio of 4 implies that 4 data samples are to be sampled per bit time period. If there are 16 parallel sampling circuits which sample input data based on clock data, 16 equally spaced clock phases are required. This proliferation of clocks can be expensive in hardware and power, and the majority of the samples collected are not actually used for extracting transmitted data samples.
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International Search Report for International Application No. PCT/US01/50149 dated Apr. 23, 2002.
Kim Ook
Li Hung Sung
Perkins Coie LLP
Silicon Image
Tse Young T.
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