Clock and data recovery circuit without jitter peaking

Details Clock and data recovery circuit without jitter peaking Clock and data recovery circuit without jitter peaking

2007-06-05

2007-06-05

Tran, Khanh (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

Reexamination Certificate

active

09888717

ABSTRACT:
In a clock recovery circuit, the output clock from a voltage controlled oscillator is delayed and then provided to a phase detector circuit that generates a difference signal indicating the phase difference between an incoming data stream and the delayed output clock. A loop filter circuit receives the difference signal and supplies a control signal to the oscillator circuit, which varies the output clock according to the control signal. A delay clock circuit receives a delay control signal derived from the difference signal to determine the output clock delay.

REFERENCES:
patent: 4647984 (1987-03-01), Suzuki et al.
patent: 5036298 (1991-07-01), Bulzachelli
patent: 6118316 (2000-09-01), Tamamura et al.
patent: 6178212 (2001-01-01), Akashi
patent: 6229357 (2001-05-01), Nair et al.
patent: 6353648 (2002-03-01), Suzuki
patent: 6542040 (2003-04-01), Lesea
patent: 6711227 (2004-03-01), Kaylani et al.
patent: 6959062 (2005-10-01), Stubbs

Affiliated with

Also associated with

Rating

Clock and data recovery circuit without jitter peaking does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock and data recovery circuit without jitter peaking, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock and data recovery circuit without jitter peaking will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3885893