Clock and data recovery circuit without jitter peaking

Pulse or digital communications – Receivers – Angle modulation

Reexamination Certificate

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Reexamination Certificate

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09888717

ABSTRACT:
In a clock recovery circuit, the output clock from a voltage controlled oscillator is delayed and then provided to a phase detector circuit that generates a difference signal indicating the phase difference between an incoming data stream and the delayed output clock. A loop filter circuit receives the difference signal and supplies a control signal to the oscillator circuit, which varies the output clock according to the control signal. A delay clock circuit receives a delay control signal derived from the difference signal to determine the output clock delay.

REFERENCES:
patent: 4647984 (1987-03-01), Suzuki et al.
patent: 5036298 (1991-07-01), Bulzachelli
patent: 6118316 (2000-09-01), Tamamura et al.
patent: 6178212 (2001-01-01), Akashi
patent: 6229357 (2001-05-01), Nair et al.
patent: 6353648 (2002-03-01), Suzuki
patent: 6542040 (2003-04-01), Lesea
patent: 6711227 (2004-03-01), Kaylani et al.
patent: 6959062 (2005-10-01), Stubbs

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