Clock and data recovery circuit and clock control method

Details Clock and data recovery circuit and clock control method Clock and data recovery circuit and clock control method

2007-03-06

2007-03-06

Chin, Stephen (Department: 2634)

Pulse or digital communications

Receivers

Angle modulation

C375S324000, C327S156000, C329S307000, C329S325000, C329S360000

Reexamination Certificate

active

10022551

ABSTRACT:
To provide a clock and data recovery circuit which facilitates alteration of the frequency range and adjustment of characteristics. The clock and data recovery circuit includes a phase shift circuit101having a switch receiving as inputs multi-phase clocks for selecting and outputting plural sets of the paired clocks from the input multi-phase clocks and a plural number of interpolators receiving the plural number of clock pairs output from the switch to output signals having the delay prescribed by the time corresponding to interior division of the phase difference of the clock pairs, a plural number of latch circuits102for latching the input data based on the signals output from the phase shift circuit101, a counter103for counting the outputs of the plural latch circuits, a filter105for averaging the counter output over a preset time, a decoder106for decoding an output of the filter and a selection circuit104fed with a plural number of sets of data output by the plural latch circuits and clocks output from a preset one of the plural interpolators to select pairs of output data and clocks.

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