Clock and data recovery circuit and clock control method...

Details Clock and data recovery circuit and clock control method... Clock and data recovery circuit and clock control method...

2003-05-02

2004-06-22

Nguyen, Linh M. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Regenerating or restoring rectangular or pulse waveform

C327S164000

Reexamination Certificate

active

06753712

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a clock and data recovery circuit and clock control method thereof.
BACKGROUND OF THE INVENTION
FIG. 8
is a diagram illustrating the structure of a clock and data recovery circuit according to the prior art. As shown in
FIG. 8
, the clock and data recovery circuit has a voltage-controlled oscillator (VCO)
51
of a PLL (phase Locked Loop) which generates a multiphase clock (multiphase output) of equally spaced phase differences from a reference clock (Ref CLK) applied thereto. The VCO comprises an analog ring oscillator, which is composed by an odd-number of inverter circuits connected into a ring-shaped configuration. A multiphase clock of equally spaced phase differences is extracted differentially from the outputs of differential inverting circuits constructing the ring oscillator. The clock and data recovery circuit has a plurality of flip-flops
52
(F/F
1
to F/F
8
), which have data input terminals for receiving the input data DATA commonly and clock input terminals for receiving respective clock signals of the multiphase clock output from the VCO
51
. The flip-flop
52
samples and outputs the input data DATA at a rising or falling edge of the clock signal fed to the clock input terminal.
This clock and data recovery circuit has a counter
53
, which receives the data output from each of the plurality of flip-flops
52
(F/F
1
to F/F
8
), and which counts the logic value of the data up and down, and a filter
55
which performs time-averaging of the output of the counter
53
over a predetermined time constant. The output voltage of the filter
55
is supplied as the control voltage of the VCO
51
. Some or all of the outputs of the flip-flops
52
and one phase of the clock output from the VCO
51
are output as data and a clock signal. The outputs of the plurality of flip-flops (F/F
1
to F/F
8
) are the result of sampling the data DATA by clock signals phase-shifted in small increments. The sampled waveform obtained is the result of sampling the data DATA at a frequency that is eight times the frequency of the reference clock signal. The timing of the clock signal of a flip-flop for which the output value does not agree with the output value of the neighboring flip-flop is the transition point of the data DATA (this point is also referred to as the “data changeover portion”).
If the clock signal lags with respect to the data transition time point (i.e., if latch timing is lagging), the value of the counter
53
is counted up to advance the phase of the clock signal. If the clock leads the data transition time point (i.e., if the latch timing is leading), the value of the counter
53
is counted down to delay the phase of the clock signal. It should be noted that the counter
53
may comprise a charge pump (CP) for charging a capacitor with a constant current when the output value of each of the plurality of flip-flops (F/F
1
to F/F
8
) is logic “0”, and discharging the capacitor with a constant current when the output value is logic “1”.
See Reference
1
(ISSCC 1997 pp. 238-239, Alan Fiedler, “A 1.0625 Gbps Transceiver with 2×-Oversampling and Transmit Signal Pre-Emphasis”), which is an example of the clock and data recovery circuit shown in FIG.
8
. The clock and data recovery circuit described in Reference
1
has a receiver circuit for recovering a clock and data from input data and outputting resulting data as parallel data. The VCO of a PLL (Phase-Locked Loop) has a 10-delay-stage ring oscillator, and the VCO
20
clock phases provide 2× oversampling clock signals to the receiver circuit to recover a clock and data. The receiver circuit locks the VCO to the input data and recovers a clock from an NRZ (Non-Return to Zero) transition. The clock and data recovery circuit described in Reference 1 has a data phase detector that comprises a plurality of high-speed latches and exclusive-OR gates for detecting coincidence
on-coincidence of the high-speed latches. A Latch that samples data bits is clocked by the non-inverted clock signal of the VCO, and a latch that samples the boundary between data bits is clocked by the inverted clock signal of the VCO.
In the conventional circuit shown in
FIG. 8
, the multiphase clock is generated by the VCO, and a phase interpolator comprising an analog circuit is used as an interpolator.
In the specification of Japanese Patent Application No. 2000-389526 (Japanese Patent Kokai Publication JP-A-P2002-190724A), the present Inventor proposes an arrangement, which is shown in
FIG. 9
, as a clock and data recovery circuit for facilitating a change in frequency range, facilitating adjustment of characteristics and varying the number of parallel data and clock outputs. This clock and data recovery circuit comprises a plurality of latch circuits
102
to which input data is supplied in common; a phase-shift circuit
101
A for generating clock signals, which are phase-shifted from one another, supplied to respective ones of the latch circuits; a counter
103
the count of which is counted up and down based upon the outputs of the plurality of latch circuits
102
; a filter
105
for smoothing the output of the counter
103
; and a decoder
106
which receives the output of the filter
105
as an input, and decodes the received signal to deliver a signal, which controls the phases of the clock signals, to the phase-shift circuit
101
A. On the basis of the output from filter
105
, the decoder
106
delays the phases of clock signals CKL
1
to CLK
8
incrementally whenever the output of counter
103
is incremented.
The clock and data recovery circuit shown in
FIG. 9
latches data successively phase by phase using a multiphase clock (eight phases in
FIG. 9
) the frequency of which is less than that of the data rate. The relationship among the data rate, the frequency of the multiphase clock and the number of phases generally is expressed as follows in approximate fashion:
(data rate)=(frequency of multiphase clock)×(number of phases)/
K
  (1)
where K represents a number indicating the number of clock phases by which the width of one bit of data is clocked. In the implementation of
FIG. 9
, K=2 holds. More specifically, as indicated in the timing diagram of
FIG. 11
, the data transition time point (the data changeover portion that is the boundary between data bits in the case of the NRZ waveform) and data bit (value of the data) are sampled at two phases.
In the circuit shown in
FIG. 9
, the results of latching the width of one bit of data at the edges of a plurality of clock signals are compared using the up/down counter
103
, thereby detecting the transition time point at which the data changes, phase lead/lag of the data and clock is discriminated, and a signal specifying up (for advancing the clock relative to the data) or down (for delaying the clock relative to the data) is output.
The output of the up/down counter
103
is supplied to the filter circuit
105
. The latter operates on the up/down signal and, if the magnitude of count-up, count-down exceeds a fixed value, outputs a signal to the decoder
106
so as to advance or delay the clock phase.
This conventional clock and data recovery circuit is so adapted that the clock signals of the multiphase clock are shifted in unison in the phase-shift circuit
101
A.
FIG. 10
is a diagram illustrating the structure of the phase-shift circuit
101
A depicted in FIG.
9
. As shown in
FIG. 10
, the phase-shift circuit
101
A comprises a switch
110
, to which the 8-phase clock is input, for selecting and outputting a plurality of pairs of two mutually adjacent clock signals from the 8-phase clock, and a plurality of interpolators
111
(Int. 1 to Int. 8), which receive plurality of clock pairs output from the switch
110
, and output signals in which delay time is stipulated by time obtained by performing interior division of the phase difference between the clock signals of the pair. In a case where the output of the counter
103
is, e.g., eight bits, a signal U of, e.g., the four h

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