Clock and data recovery circuit

Details Clock and data recovery circuit Clock and data recovery circuit

2011-03-22

2011-03-22

Wang, Ted M (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S326000, C375S354000, C375S373000, C375S376000

Reexamination Certificate

active

07912167

ABSTRACT:
A clock and data recovery circuit includes a four-phase generation circuit that generates four-phase clock signals with phases thereof being equally spaced by 90 degrees, a first interpolator and a second interpolator, each of which receives two of the clocks with phases thereof separated to each other by 180 degrees, performs phase interpolation, and outputs a signal obtained by the interpolation and a signal with a phase reverse to a phase of the interpolated signal. A four-phase to eight-phase conversion circuit receives the four-phase clocks from the first and second interpolators, buffers the four-phase clock signals output from the first interpolator and the second interpolator and outputs the buffered four-phase clock signals without alteration, and generates four-phase clocks each obtained by interpolation of two of the clock signals with the mutually adjacent phases among the four-phase clock signals output from the first interpolator and the second interpolator.

REFERENCES:
patent: 6564359 (2003-05-01), Saeki
patent: 6753712 (2004-06-01), Saeki
patent: 7116744 (2006-10-01), Saze et al.
patent: 2002/0079938 (2002-06-01), Saeki
patent: 2002/0172304 (2002-11-01), Saze et al.
patent: 1246388 (2002-10-01), None
patent: 2002-190724 (2002-07-01), None
German Office Action date Jun. 2, 2008 (English Translation).

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