Clock adjusting circuit and semiconductor integrated circuit...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input

Reexamination Certificate

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Reexamination Certificate

active

08072253

ABSTRACT:
Disclosed is a clock adjusting circuit comprising a phase shifter that receives a clock signal and variably shifts, based on a control signal, respective timing phases of a rising edge and a falling edge of the clock signal; and a control circuit that supplies the control signal to the phase shifter circuit before each edge is output; wherein the clock signal, in which at least one of a period, a duty ratio, jitter and skew/delay of the input clock signal is changed over an arbitrary number of clock cycles, is output.

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patent: 6028461 (2000-02-01), Kobayashi
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6127858 (2000-10-01), Stinson et al.
patent: 6806750 (2004-10-01), Rasmussen et al.
patent: 6891421 (2005-05-01), Slawecki
patent: 7065172 (2006-06-01), Xiu et al.
patent: 2003/0065962 (2003-04-01), Lim et al.
patent: 2006/0294410 (2006-12-01), Kizer et al.
patent: 09-186682 (1997-07-01), None
patent: 11-024783 (1999-01-01), None

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