Clock adjusting circuit and method to adjust a delay value of a

Details Clock adjusting circuit and method to adjust a delay value of a Clock adjusting circuit and method to adjust a delay value of a

1998-06-26

2000-02-22

Zweizig, Jeffrey

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327160, 327161, H03L 706

Patent

active

060284617

ABSTRACT:
A clock adjusting circuit is disclosed which is able to adjust automatically both the phase and pulse width of a balanced transmission clock, to be coincident with the reference clock. Phase comparison circuits 13, 14 detect the difference between the phase of a reference clock (REF) and a feedback signal of the clock output. Counters 15, 16 count based on the difference detected by the phase comparison circuits 13, 14, respectively. Delay circuits 11, 12 delay the clock input signals based on the counted value by the counters 15, 16. Clock output signal is obtained after selecting, by the selector 23, the result of OR or AND of the outputs of the delay circuit 11, 12.

REFERENCES:
patent: 5142555 (1992-08-01), Whiteside
patent: 5646564 (1997-07-01), Erickson et al.
patent: 5675273 (1997-10-01), Masleid
patent: 5757218 (1998-05-01), Blum
patent: 5811998 (1998-09-01), Lundberg et al.

Affiliated with

Also associated with

Rating

Clock adjusting circuit and method to adjust a delay value of a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Clock adjusting circuit and method to adjust a delay value of a , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock adjusting circuit and method to adjust a delay value of a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-523461