Clock adapter using a phase locked loop configured as a frequenc

Details Clock adapter using a phase locked loop configured as a frequenc Clock adapter using a phase locked loop configured as a frequenc

1990-04-26

1991-10-22

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 331 34, 331 57, 331179, H03L 7099, H03L 718

Patent

active

050599240

ABSTRACT:
A phase locked loop configured as a frequency multiplier capable of nonintegral feedback path division utilizes a multiphase voltage controlled oscillator (5) which generates a plurality of signals (10a-10f) having a substantially identical frequency but each offset equally from the other by a given phase angle. A commutator (3) selects signals of adjacent phases so as to give the time average output signal (9) a frequency higher or lower than the frequency 10a-10f. Frequency translation is accomplished by periodically selecting signals having a longer or shorter period as desired so that a commutator output signal (9) is delayed or advanced by an appropriate amount. In the preferred embodiment, the phase locked loop is capable of converting a 1.544 MHz signal to a 2.048 MHz signal or vice versa.

REFERENCES:
patent: 3731219 (1973-05-01), Mader et al.
patent: 4091335 (1978-05-01), Giolma et al.
patent: 4584695 (1986-04-01), Wong et al.

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