Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Electromagnetic or particle radiation
Reexamination Certificate
2001-05-09
2002-08-27
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Electromagnetic or particle radiation
C257S215000, C257S222000
Reexamination Certificate
active
06441453
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention is directed to an economical chip package for an imager integrated circuit (IC) chip. More precisely, the invention is directed to an economical package and combination of coating and cap for imager circuitry contained in an integrated circuit (IC) chip, such as a CMOS (Complimentary Metal Oxide Semiconductor) imager.
2. Related Art
Conventional chip packages are made with a number of techniques. First, one type of popular chip carrier is one known as a ceramic-leaded chip carrier (CLCC). Other types of chip packages include a plastic leadless chip carrier (PLCC), multi-layer ceramic pin grid ray (PGA) package, and ball grid ray (BGA) type packages. The PLCC and CLCC packages typically contain leads at the edge of the carrier. Most imagers, for example, utilize PLCC and CLCC packaging. The PGA and BGA packages typically contain leads on the bottom of the carrier in an array pattern.
In all these chip carrier packages, the basic principals remain the same. First, an IC chip is mated to the package substrate. The package substrate contains interconnections consisting of metallic traces that couple electric connections on the IC chip to leads on or in the chip package itself. As such, the IC chip is electrically connected to the external environment through the metallic traces and the leads present on the chip carrier package.
In the mating process for the chip carrier to the IC chip, the relative distances and areas used for the electrical interconnections are small. Thus, when a high-speed digital or analog line is close to another electrical line, high switching speeds or frequencies can create interference between the neighboring due to parasitic capacitance or inductance. The limited geometries of typical chip carrier packages inhibit the minimization of these problems.
Such problems are compounded with imager packaging. For example, as the resolution of CMOS (Complementary Metal Oxide Semiconductor) imager sensor cores increase, attempting to successfully design and package such imagers becomes increasingly difficult due to the corresponding increase in sensitivity to parasitic capacitance and inductance inherent in the package.
A cap or cover is employed to protect IC chips from the external environment. Typically a cap or cover, which may be made of a ceramic type material, for example, is bonded into place on the package made of the IC chip connected to the ceramic substrate. The ceramic materials are typically used to seal caps and covers to the module substrate. The ceramic type materials are also used to seal pin feed-through in the chip carrier modules.
Ceramic module sealing is typically used when the substrate and the cover are ceramic. The sealing materials are based on glasses with low melting temperatures since the sealing temperatures must not degrade the devices within the module. Typical sealing temperatures are in the range of 400° to 500° C. The glass is normally ground into a powder, then mixed into a paste with organic binders and saltants. The paste is applied to the seal areas by screening, stenciling, or extrusion, and the made in substrate cover (with mounted IC enclosed) are heated to flow the glass in former hermetic seal.
Glass is also used to fasten and seal through holes in the carrier modules. Short tubes of the glass sealing material are placed over the pins. Then the case, with the pins and preforms, is placed in a fixture for joining. The joining is accomplished by melting the glass, which then bonds to the pins and the case. Since this operation is performed before any of the devices are mounted to the module, the sealing temperatures are only limited by the properties of the case and the pins, and can be much higher than for module sealing.
Good properties of a sealing material include: the ability to form a hermetic seal; electrically insulating to prevent shorting; ability to wet the mating materials at the sealing temperature; and the ability to inhibit movement or stresses placed on the bonding of the IC chip to the substrate when in use due to thermal expansion.
In normal applications, the resulting chip and carrier is mated to a board that can itself be mated to another device. The board is typically a printed circuit board or the like. The card or planar surface has pads or holes to accept the terminals from the module. For LCC components, the connection points are pads. In the case of PGA components and dual inline packages (DIP), the pins interface into plated through holes in printed circuit boards. In both cases, the pins are soldered into place.
Typically, printed circuit boards consist of interleaved layers of conducting and insulating material. The insulating material may be such material as an epoxy/glass or a fiberglass surface, for example. The insulating surface is typically washed in a bath of conductive material to deposit a conductive layer on top of the insulating layer. Then, a circuitization step is accomplished using photoresist protecting the interconnection lines. The resulting traces form the electrical interconnects on the printed circuit board.
Many such layers can be combined through the use of plated through holes, or vias. In this manner, three-dimensional routing may be formed and routed. As such, the connection of a functional IC chip to an electronic device usually involves at least two different connection processes. First, the IC chip is typically mounted and electrically connected within a package, e.g., within a ceramic chip package. Next, the imager IC package is electrically coupled to a printed circuit for final insertion into the electronic device.
This multi-stage process is expensive, cumbersome and subject to failure. Specifically, the plurality of steps of electrical interconnection allow for a greater probability of failure because of a failure in the electrical interconnections between the IC chip and the imager IC package, or between the electrical package containing the IC chip and each board layer.
Additionally, the process of constructing a package contains many steps and uses relatively expensive materials. In a mass-market consumer market, a single type of packaged IC's may be distributed and used by the millions. For example, an imager IC chip may be employed across a wide spectrum of mass market items, such as digital cameras, security devices, communications devices, digital camcorders, and devices used in streaming web technology, just to name a few. The ease and cost of manufacturing these imagers is important in IC chips employed in such wide usage.
Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.
SUMMARY OF THE INVENTION
Various aspects of the present invention can be found in a package for an imager chip containing an integrated circuit. The imager chip has an electrical contact that transmits an electrical signal to or from the integrated circuit.
The package is made with a base insulating substrate, made out of a glass epoxy or laminate, such as a printed circuit board. The base insulating substrate is preformed with bond pads and electric leads. The bond pads are electrically coupled to the leads.
A imager chip is mated to the base insulating substrate, with the electrical contacts of the imager chip coupled to the bond pads when properly in place. Or, the bond pads may be coupled to the electrical contacts in a succeeding step. This allows transmission of an electrical signal between the leads and the integrated circuit, through the bond pad and the electrical interconnects on the preformed base insulating substrate.
Additionally, a retaining structure is constructed on the base insulating substrate, such that the retaining structure encircles the imager chip. Thus, the retaining structure and the planar surface of the base insulating substrate form a recess, in which the imager chip is mated to the base insulating substrate. The retaining structure may be made of an epo
Akin Gump Strauss Hauer & Feld & LLP
Conexant Systems Inc.
Nelms David
Nguyen Thinh
LandOfFree
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