Class D amplifier with reduced clock requirement and related met

Details Class D amplifier with reduced clock requirement and related met Class D amplifier with reduced clock requirement and related met

1998-02-06

2000-01-11

Pascal, Robert

Amplifiers

Modulator-demodulator-type amplifier

330251, H03F 338

Patent

active

060140550

ABSTRACT:
A class D amplifier includes a separating circuit for separating a pulse code modulation (PCM) signal into a K least significant bits (LSBs) signal and an L most significant bits (MSBs) signal; a PCM to pulse width modulation (PWM) converter for converting the L MSBs signal into a PWM signal; and an LSB processor for proportionally altering the PWM signal from the PCM to PWM converter based upon the K LSBs signal to define a PWM output control signal. More particularly, the PCM input signal may be an N-1 bit PCM magnitude signal. The amplifier preferably further includes a sign and magnitude extraction circuit for extracting a sign bit signal and the N-1 bit magnitude signal from an N bit two's complement PCM input signal. Accordingly, the class D amplifier may also include a switch driver responsive to the extracted sign bit signal and the PWM output control signal, such as to control polarity and on time, respectively. The PCM to PWM converter may be one of a symmetric PCM to PWM converter; a trailing edge PCM to PWM converter; and a leading edge PCM to PWM converter. Thus, the LSB processor circuit is preferably adapted for cooperating with the respective type of PCM to PWM converter.

REFERENCES:
patent: 3789393 (1974-01-01), Tripp
patent: 3893102 (1975-07-01), Candy
patent: 4006475 (1977-02-01), Candy et al.
patent: 4390849 (1983-06-01), Miskin
patent: 4590457 (1986-05-01), Amir
patent: 4673887 (1987-06-01), Atherton

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