Class AB operational amplifier with split folded-cascode...

Details Class AB operational amplifier with split folded-cascode... Class AB operational amplifier with split folded-cascode...

2003-06-19

2004-12-07

Nguyen, Patricia (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S255000, C330S257000

Reexamination Certificate

active

06828855

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to class AB operational amplifiers, and more particularly to a class AB operational amplifier having a split folded-cascode structure.
In a typical “folded mesh” type of class AB amplifier structure, bias current in the output transistors is not well-controlled, especially when the structure is used in circuit designs that are not low-power, low voltage designs.
The article “Compact Low-Voltage Power-Efficient Operational Amplifier Cells for VLSI” by De Langen and Huijsing, (IEEE JSSC volume 33, No. 10, October 1988) describes a rail-to-rail operational amplifier including a class AB output stage having “folded mesh” feedback control circuitry. “Prior Art”
FIG. 1
herein is taken from the foregoing article and shows a simplified schematic diagram for the described operational amplifier in which a circuit branch connected to the drain of the current mirror transistor M
10
is “split” into above folded mesh circuitry, which includes transistors M
13
-
16
. (A conventional folded cascode structure would eliminate transistors M
13
and M
16
.) The folded mesh circuitry produces differential output signals, one of which drives the gates of output transistor M
1
and a corresponding output current sensing transistor M
11
. The other one of the differential output signals drives the gates of output transistor M
2
and a corresponding current sensing transistor M
12
, which is used to provide class AB control feedback. The current in output transistor M
1
is sensed by transistor M
11
to provide a corresponding input signal to the class AB control circuit, and the current in output transistor M
2
is sensed by transistor M
12
to provide a corresponding input signal to the class AB control circuit.
The resulting output voltage VAB produced by the class AB control circuit is applied as a feedback loop control signal to the gate of cascode transistor M
16
. The voltage VAB is compared to the gate voltage of transistor M
14
, which is developed across transistor M
18
by the flow of reference current I
18
through diode-connected transistor M
18
. The quiescent output current through output transistors M
1
and M
2
is a design parameter that can be controlled by the choice of the value of reference current I
18
, the ratio of the channel-width-to-channel-length of current sensing transistor M
11
to that of output transistor M
1
, and the ratio of the channel-width-to-channel-length of current sensing transistor
12
to that of output transistor M
2
.
The circuitry of prior art
FIG. 1
works very well with low values of the supply voltage VDD, e.g. 2 volts. However, in situations in which a higher value of VDD is required, e.g. 5 volts, the circuit of
FIG. 1
tends to produce inadequate control of the quiescent bias current through the output transistors M
1
and M
2
. The inadequate bias current control is due to the fact that the differential class AB drive voltage signals produced by the folded mesh circuitry and applied to the gates of output transistors M
1
and M
2
can differ by as much as 3 volts at larger values of VDD. The folded mesh circuitry and class AB control a loop in of
FIG. 1
is quite sensitive to VDD. For VDD equal to approximately 2 volts, the quiescent bias current in the output transistors is fairly controllable, but if VDD is increased to approximately 5 volts, the quiescent bias current in the output stage will increase substantially, which results in substantially increased power consumption of the operational amplifier. The undesirable increase in the quiescent output bias current through output transistors M
1
and M
2
occurs because the difference between their gate voltages increase as the supply voltage VDD increases. In order to achieve precise control of the quiescent output bias current, the class AB control loop needs to the attenuate the foregoing gate voltage difference, which is referred to as the “systematic error”. Unfortunately, the class AB loop gain for the circuit of
FIG. 1
is relatively low. If the properties of the folded mesh cascode circuit structure including transistors M
13
-
16
is examined, it can be seen that only the common mode signals in the folded mesh circuitry obtain the same benefit as the main amplifier signals from the cascode circuit. However the class AB control loop structure presents a differential feedback signal in the folded mesh circuitry, and each pair of cascode transistors is source-coupled and consequently loses the main benefit of using cascode transistors. The resulting lower impedance in the class AB control loop in turn results in a lower class AB loop gain, and this results in a reduced ability to the attenuate the above-mentioned systematic errors. The gain of the class AB control loop is poor, which causes poor control of, and consequently instability of, the quiescent bias current flowing through output transistors M
1
and M
2
.
Thus, there is an unmet need for a class AB output stage that provides a highly controllable quiescent bias current in the output transistors at relatively high power supply voltages and at relatively low power supply voltages.
There also is an unmet need for a class AB output stage that provides a highly controllable quiescent bias current in the output transistors over a fairly broad range from relatively low power supply voltages to relatively high power supply voltages with no additional cost or complexity compared to that of a typical prior art folded mesh type of class AB output stage circuit.
There also is an unmet need for a class AB control feedback loop that more effectively attenuates a reduces the systematic error associated with the folded mesh circuitry of the closest prior art in order to accomplish accurate control of the quiescent bias current flowing through the output transistors of a class AB output stage.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a class AB output stage that provides a highly controllable quiescent bias current in the output transistors at relatively high power supply voltages and at relatively low power supply voltages.
It is another object of the present mentioned to provide a class AB output stage that provides a highly controllable quiescent bias current in the output transistors over a fairly broad range from relatively low power supply voltages to relatively high power supply voltages with no additional cost or complexity compared to that of a typical prior art folded mesh type of class AB output stage circuit.
It is another object of the present invention to provide a class AB control feedback loop that more effectively attenuates (reduces) the systematic error associated with the folded mesh circuitry of the closest prior art in order to accomplish accurate control of the quiescent bias current flowing through the output transistors of a class AB output stage.
Briefly described, and in accordance with one embodiment, the present invention provides circuitry for controlling quiescent bias current in output transistors of a class AB output stage is controlled by providing substantially equal amounts of differential amplification to both an output of a differential input stage (
2
) of an amplifier and an output (
17
,
18
) of a class AB control circuit (
46
) of the amplifier. A split input transistor circuit structure for a first side of the differential input stage (
2
) includes first (
15
) and second (
16
) input transistors with gates coupled to a first input (Vin+) of the amplifier. A third input transistor (
10
) of the input stage has a gate coupled to a second input (Vin−) of the amplifier. A split folded cascode circuit structure having a common gate configuration includes first (
25
) and second (
30
) cascode transistors having their gates coupled to a reference voltage and their drains coupled to the first (
26
) and second (
37
) gate drive conductors, respectively, and a third cascode transistor (
22
) has a gate connected to the reference voltage and a source coupled to a drain of the

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