Clamping video signals

Details Clamping video signals Clamping video signals

1982-08-12

1984-09-25

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

H04N 518

Patent

active

044738463

ABSTRACT:
A video signal clamping circuit comprises a summing circuit (R1, R2, R9, 2) an analogue to digital converter (3), a programmable read only memory (6), a latch (7), a digital to analogue converter (9) and an integrator (11). The PROM (6) is addressed by the ADC(3) and produces a 4 bit output code which is dependent on the amplitude of the video signal. This is stored on the latch (7) and passed to the DAC(9) during a timing pulse applied to terminal (8) which occurs during the line blanking period. The DAC(9) produces an output which is stored on the capacitor (C1) in the integrator (11). The integrator (11) output is summed with the input video signal to clamp the video signal level to the reference voltage so that a clamped digital video signal is available from the output (5).

REFERENCES:
patent: 3736370 (1973-05-01), Thielking
patent: 4178610 (1979-11-01), Constable et al.
patent: 4183050 (1980-01-01), Tsuchiya et al.
patent: 4261015 (1981-04-01), Dakroub
patent: 4415929 (1983-11-01), Yoshisato

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