Clamping circuit with wide input dynamic range for video or...

Details Clamping circuit with wide input dynamic range for video or... Clamping circuit with wide input dynamic range for video or...

2006-04-04

2006-04-04

Lee, Michael H. (Department: 2614)

Television

Image signal processing circuitry specific to television

Dc insertion

C348S691000

Reexamination Certificate

active

07023497

ABSTRACT:
A clamping circuit disclosed herein has two modes of operation which include both a bottom level and mid-level clamping mode for clamping automatically onto the sync tip of a video signal and customizably clamping onto the front porch, back porch/pedestal or anywhere within the signal. The clamping circuit (400) includes a clamping capacitor (404) that couples to an automatic clamping circuit portion (405) to automatically clamp the synchronization pulse of the video input signal to a first predetermined reference voltage (Vref1) of a first clamping pulse signal during an automatic clamping mode of operation. The automatic clamping portion (405) connects to the customizable clamping circuit portion (411) to clamp any portion of the video input signal to a second predetermined reference voltage (Vref2) of a second clamping pulse signal during a customizable clamping mode of operation. A buffer (416) connects between the customizable clamping circuit portion and the output node of the clamping circuit.

REFERENCES:
patent: 4114179 (1978-09-01), Ilieve
patent: 5260794 (1993-11-01), Sase et al.
patent: 5508749 (1996-04-01), Matsuo
patent: 5760844 (1998-06-01), Jorden
patent: 5986719 (1999-11-01), Nakamura
patent: 5995166 (1999-11-01), Kawano
patent: 6204892 (2001-03-01), Kawano

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