Clamping circuit for use in computer system

Electricity: electrical systems and devices – Safety and protection of systems and devices – Voltage regulator protective circuits

Reexamination Certificate

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Details

C361S018000

Reexamination Certificate

active

06721150

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a clamping circuit in a computer system. More particularly, this invention relates to a clamping circuit used in a computer system to prevent damage or erroneous behavior caused by voltage spikes and other over-voltage conditions.
2. Description of the Related Art
The components used in computer systems are designed to be operated within certain ranges. If a component is operated outside of its tolerated range, its reliability may be greatly reduced. In certain circumstances, the component may even be destroyed. Electrical noise in computer systems may cause voltage spikes and other over-voltage conditions. These voltage spikes and over-voltage conditions may cause damage to components in the computer system. Even if these conditions do not damage the components, the over-voltage conditions may still cause data loss or improper operation. For example, noise may cause logic gates or other devices to produce erroneous output signals.
Turning now to
FIG. 1
, a block diagram of one embodiment of a computer system
100
including processor
10
coupled to a variety of system components through a bus bridge
102
is shown. Other embodiments are possible and contemplated. In the depicted system, a main memory
104
is coupled to bus bridge
102
through a memory bus
106
, and a graphics controller
108
is coupled to bus bridge
102
through an AGP bus
110
. Finally, a plurality of PCI devices
112
A-
112
B are coupled to bus bridge
102
through a PCI bus
114
. A secondary bus bridge
116
may further be provided to accommodate an electrical interface to one or more EISA or ISA devices
118
through an EISA/ISA bus
120
. Processor
10
is coupled to bus bridge
102
through a CPU bus
124
and to an optional L
2
cache
128
.
Bus bridge
102
provides an interface between processor
10
, main memory
104
, graphics controller
108
, and devices attached to PCI bus
114
. When an operation is received from one of the devices connected to bus bridge
102
, bus bridge
102
identifies the target of the operation (e.g. a particular device or, in the case of PCI bus
114
, that the target is on PCI bus
114
). Bus bridge
102
routes the operation to the targeted device. Bus bridge
102
generally translates an operation from the protocol used by the source device or bus to the protocol used by the target device or bus.
In addition to providing an interface to an ISA/EISA bus for PCI bus
114
, secondary bus bridge
116
may further incorporate additional functionality, as desired. An input/output controller (not shown), either external from or integrated with secondary bus bridge
116
, may also be included within computer system
100
to provide operational support for a keyboard and mouse
122
and for various serial and parallel ports, as desired An external cache unit (not shown) may further be coupled to CPU bus
124
between processor
10
and bus bridge
102
in other embodiments. Alternatively, the external cache may be coupled to bus bridge
102
and cache control logic for the external cache may be integrated into bus bridge
102
.
12
cache
128
is further shown in a backside configuration to processor
10
. It is noted that L
2
cache
128
may be separate from processor
10
, integrated into a cartridge (e.g. slot
1
or slot A) with processor
10
, or even integrated onto a semiconductor substrate with processor
10
.
Main memory
104
is a memory in which application programs are stored and from which processor
10
primarily executes. A suitable main memory
104
comprises DRAM (Dynamic Random Access Memory). For example, a plurality of banks of SDRAM (Synchronous DRAM) or Rambus DRAM (RDRAM) may be suitable. PCI devices
112
A-
112
B are illustrative of a variety of peripheral devices such as, for example, network interface cards, video accelerators, audio cards, hard or floppy disk drives or drive controllers, SCSI (Small Computer Systems Interface) adapters and telephony cards. Similarly, ISA device
118
is illustrative of various types of peripheral devices, such as a modem, a sound card, and a variety of data acquisition cards such as GPIB or field bus interface cards.
Graphics controller
108
is provided to control the rendering of text and images on a display
126
. Graphics controller
108
may embody a typical graphics accelerator generally known in the art to render three-dimensional data structures which can be effectively shifted into and from main memory
104
. Graphics controller
108
may therefore be a master of AGP bus
110
in that it can request and receive access to a target interface within bus bridge
102
to thereby obtain access to main memory
104
. A dedicated graphics bus accommodates rapid retrieval of data from main memory
104
. For certain operations, graphics controller
108
may further be configured to generate PCI protocol transactions on AGP bus
110
. The AGP interface of bus bridge
102
may thus include functionality to support both AGP protocol transactions as well as PCI protocol target and initiator transactions. Display
126
is any electronic display upon which an image or text can be presented. A suitable display
126
includes a cathode ray tube (“CRT”), a liquid crystal display (“LCD”), etc.
It is noted that, while the AGP, PCI, and ISA or EISA buses have been used as examples in the above description, other bus architectures are also known. It is further noted that computer system
100
may be a multiprocessing computer system including additional processors (e.g. processor
10
a
shown as an optional component of computer system
100
). Processor
10
a
may be similar to processor
10
. More particularly, processor
10
a
may be an identical copy of processor
10
. Processor
10
a
may be connected to bus bridge
102
via an independent bus (as shown in
FIG. 1
) or may share CPU bus
124
with processor
10
. Furthermore, processor
10
a
may be coupled to an optional L
2
cache
128
a
similar to L
2
cache
128
.
Computer system
100
may require many different voltages. For example, in a split rail design, the core circuitry of the microprocessor may require a different voltage than the I/O circuitry of the microprocessor. Other circuitry in the computer system may require additional voltages as well. These voltages may be supplied by devices such as linear regulators or switching regulators. Various components in computer system
100
may also have strict requirements regarding the quality of these input voltages in order to ensure that their proper operation.
Linear regulators provide admirable dynamic-load response in low-voltage, high-current environments like computer system
100
. Because they use a simplified design, linear regulators are low cost devices. However, linear regulators are fairly inefficient, consuming a great deal of power and generating an undesirable amount of heat. There is a current trend to lower voltages and increase current in computer systems, making linear regulators' disadvantages even more apparent.
Switching regulators typically work by passing an input voltage through an input switch that is intermittently turned on and off. Because the switch frequently turns off, only a small amount of power is lost during conversion. Consequentially, switching regulators are much more efficient than linear regulators and generate much less heat. The input switching produces a waveform that can be transformed, rectified and smoothed to produce a DC output voltage. By adjusting the duty cycle of the input switch, the regulated output voltage can be controlled to lie within a certain range. Because switching regulators are very efficient, they are popular in computer systems. However, one commonly encountered drawback to using a switching regulator is that it may introduce noise into the input voltage supplied to the switching unit. For example, this noise may be a ripple at the switching frequency, or it may be radiated noise from switching currents in the regulator at the switching frequency and its harmon

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