Television – Camera – system and detail – Combined image signal generator and general image signal...
Reexamination Certificate
1999-09-17
2003-08-12
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Combined image signal generator and general image signal...
C348S241000
Reexamination Certificate
active
06606118
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clamping circuit used for a correlation-double sampling (CDS) of a pixel signal output from a solid-state imaging apparatus.
2. Description of the Related Art
Various types of solid-state imaging apparatuses such as a CCD type apparatus, a CMOS type apparatus and the like have been proposed and put into practice. It is conventionally known that, in such apparatuses, the correlation double sampling (CDS) is extremely effective in suppressing noises of pixel signals including a black level and a signal level. In the correlation double sampling, the black level of each pixel signal is clamped at a clamping potential and then, during a signal level period, the clamping is released and a variation from the black level to the signal level is sampled and held.
For example, in the CCD type imaging apparatus, since a reset noise is generated for each pixel signal in correlation with the black level and the signal level, the reset noise can be removed by the above-described CDS operation. In the CMOS type imaging apparatus, since a fixed pattern noise is generated in correlation with the black level and the signal level, the fixed pattern noise can also be removed by the CDS operation. Furthermore, in any type of solid-state imaging apparatus, although a MOS type output amplifier is likely to generate a noise within a low frequency range, the low frequency noise can be suppressed by a CDS operation because there is a correlation between a black level and a signal level corresponding to each other.
In order to achieve this CDS operation, specialized elements other than the CCD are frequently used in the CCD type imaging apparatus. Therefore, the CCD type imaging apparatus results in a complicated circuit configuration in connection with a clamping circuit and a sample-hold circuit. For the CMOS type imaging apparatus, a relatively simple circuit configuration is proposed because the CCD and the CDS circuit can be easily integrated.
There is an example of the clamping circuit using a clamping capacitance and an inverting amplifier, which is described in Japanese Laid-Open Publication No. 5-207220. This publication discloses a technology for reducing a variation of each inverting amplifier by using a plurality of inverting amplifiers. However this technique does not directly relate to the present invention; therefore, a description thereof is omitted, except specific features of the clamping circuit shown in
FIGS. 6A
to
6
C.
FIG. 6A
is a block diagram showing the entirety of a clamping circuit.
FIG. 6B
is a circuit diagram showing an inverting amplifier in the clamping circuit.
FIG. 6C
is a graph for illustrating an operation of the inverting amplifier.
As shown in
FIG. 6B
, an inverting amplifier
102
includes a combination of n-type MOSFETs
111
and
112
. In the inverting amplifier
102
, where threshold values of FETs
111
and
112
are V
T1
, and V
T2
, respectively, the following expressions (1) are satisfied:
Vo>Vi−V
T1
, V
D
−Vo>V
D
−Vo−V
T2
(1)
where Vi represents an input voltage (a pixel signal from a solid-state imaging apparatus), Vo represents an output voltage of a clamping circuit
101
, and V
D
represents a power source voltage.
Under the conditions defined by the expressions (1), FETs
111
and
112
operate in a saturation region. In this case, currents I
D
flowing in the FETs
111
and
112
are equal, so that the following expression (2) is satisfied:
K×
(
W
1
/L
1
)×(
Vi+V
T1
)
2
=K
×(
W
2
/L
2
)×(
V
D
−Vo−V
T2
)
2
(2)
where K represents a transconductance parameter, W
1
and W
2
represent channel widths of the FETs
111
and
112
, respectively, and L
1
and L
2
represent channel lengths of the FETs
111
and
112
, respectively.
Furthermore, from the expression (2), the output voltage Vo of the clamping circuit
101
is represented by the following expression (3):
Vo=−&agr;×
(
Vi+V
T1
)+(
V
D
−V
T2
) (3)
where &agr;={square root over ( )}((W
1
/L
1
)/(W
2
/L
2
)).
The graph of
FIG. 6C
shows the relationship of the input voltage Vi and the output voltage Vo. In the graph of
FIG. 6C
, a linear portion
121
satisfies the expression (3).
In the clamping circuit shown in
FIG. 6A
, Vi=Vo=V
1
in the state that an input and an output of the inverting amplifier
102
are short-circuited.
When the FETs
111
and
112
are of an enhancement type, V
T1
>0, V
T2
>0. Therefore, when a clamping switch SW
1
is turned OFF to separate the input and the output from each other, Vi<V
1
, Vo>V
1
, which satisfy the expression (1). Thus, the FETs
111
and
112
operate in a saturation region, i.e., in the linear portion
121
of FIG.
6
C. Accordingly, a ratio of an output variation vo to an input variation vi is represented by the following expression (4):
vo/vi=−&agr;
(4)
Under the above conditions, in the clamping circuit shown in
FIG. 6A
, when the clamping switch SW
1
is turned ON by a control signal &phgr;c to short-circuit the input and the output of the inverting amplifier
102
, a clamping potential becomes V
1
. Thereafter, when the clamping switch SW
1
is turned OFF and the input signal Vi is input while maintaining the OFF-state, a DC component of the input signal Vi is cut off by a clamping capacitance Cc. In addition, an AC component of the input signal Vi, i.e., the variation vi, is amplified by the inverting amplifier
102
with a gain of −&agr;, and the variation vo is output from the inverting amplifier
102
. At this time, an output side potential of the inverting amplifier
102
is vo+V
1
. Since a value &agr; can be set at any large value as can be easily seen from the expression (3), the amplification can be carried out. Furthermore, the voltage V
1
, which is to be a clamping voltage, is always fixed at any point in the linear portion
121
of
FIG. 6C
as described above by the input-output short circuiting, whereby an optimum operation point is obtained.
Assuming that the clamping circuit shown in
FIG. 6A
is operated at a high speed at the same periodic cycle as that of a pixel signal, each of the signals in the clamping circuit varies as shown in, for example, FIG.
7
.
FIG. 7
shows the input voltage Vin (a pixel signal from the solid-state imaging apparatus). Within period T
3
of the pixel signal, period T
1
is a black level period, and period T
2
is a signal level period.
As shown in
FIG. 7
, even when the variation vi of a signal level with respect to the black level is constant in each pixel signal, the signal level varies for each pixel signal on a pixel signal-by-pixel signal basis due to a noise inherent in the solid-state imaging apparatus.
Such a noise inherent in the solid-state imaging apparatus is suppressed by the clamping operation. As shown in
FIG. 7
, during period T
4
within period T
1
, the clamping switch SW
1
is turned ON by the control signal &phgr;c to short-circuit the input and the output of the inverting amplifier
102
. The black level is then clamped at a clamping potential V
1
. Thereafter, the clamping is released, so that only the variation vi of the signal level is input to the inverting amplifier
102
through a clamping capacitance Cc. As a result, the variation vo (AC component) amplified with a gain of −&agr; by the inverting amplifier
102
is provided as shown in FIG.
7
. This suppresses the noise component of the pixel signal, so that only the signal level of the pixel signal is accurately extracted.
However, in the above conventional clamping circuit, the clamping potential includes:
1) a kTC noise introduced into the input side of the inverting amplifier
102
when the switch SW
1
is turned ON; and
2) a noise generated at the output side of the inverting amplifier made of MOSFETs.
The kTC noise 1), which is generated even in an ideal case where the inverting amplifier includes
Conlin David G.
Edwards & Angell
Garber Wendy R.
Sharp Kabushiki Kaisha
Toppin Catherine J.
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