Clamping circuit for operational amplifiers

Details Clamping circuit for operational amplifiers Clamping circuit for operational amplifiers

2007-08-07

2007-08-07

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including protection means

Reexamination Certificate

active

11181231

ABSTRACT:
A differential input operational amplifier has a voltage clamp differential transistor pair coupled to an input differential transistor pair of the operational amplifier. The voltage clamp differential transistor pair limits the output voltage of the operational amplifier by taking over control of the operational amplifier circuits from the input differential transistor pair as the output voltage approaches a clamp voltage value. A reference voltage may be used to set the output voltage at which the input differential transistor pair will be clamped by the voltage clamp differential transistor pair. Below the clamp voltage, operation of the input differential transistor pair will not be affected. At the clamp voltage the input differential transistor pair will no longer control the output of the differential amplifier, rather the voltage clamp differential transistor pair will control the maximum voltage output of the differential amplifier. Both positive and negative limiting of the operational amplifier output voltage may be accomplished.

REFERENCES:
patent: 5307024 (1994-04-01), Metz et al.
Säckinger, E. et al.; “A Versatile Building Block: The CMOS Differential Difference Amplifier”; IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987.

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