Clamping circuit for data transfer bus

Details Clamping circuit for data transfer bus Clamping circuit for data transfer bus

1989-05-22

1992-07-07

Kriess, Kevin A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307452, 307480, 307481, 307351, 307362, 307546, 365203, 365205, H03K 1920

Patent

active

051285576

ABSTRACT:
A high speed computer data transfer system includes a transistor diode clamping circuit for limiting pre-charge voltages in the case where multiple pre-charge cycles occur before a pull-down operation. Data bus voltage swings between logic high and logic low levels as well as pull-down times are reduced, thus lowering the time needed to transfer the data. Also, body effect upon the clamping circuit is lowered. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

REFERENCES:
patent: 4488066 (1984-12-01), Shoji
patent: 4498021 (1985-02-01), Uya
patent: 4572972 (1986-02-01), Shoji
patent: 4598216 (1986-07-01), Lauff et al.
patent: 4670666 (1987-06-01), Yoshida
patent: 4694432 (1987-09-01), Miyatake et al.
patent: 4761567 (1988-08-01), Walters, Jr. et al.
patent: 4763023 (1988-08-01), Spence
patent: 4885484 (1989-12-01), Gray

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