Clamping circuit for clamping video signal

Details Clamping circuit for clamping video signal Clamping circuit for clamping video signal

1988-03-09

1989-08-01

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358153, 358172, H04N 504

Patent

active

048537829

ABSTRACT:
A frame synchronizing signal detecting circuit detects a frame synchronizing signal in a video signal. When the frame synchronizing signal is not detected by the frame synchronizing signal detecting circuit, a clamp level switching circuit is responsive to a switching signal from a timer circuit for generating alternately an upper clamp potential V.sub.+ and a lower clamp potential V.sub.-. When the frame synchronizing signal is detected by the frame synchronizing signal detecting circuit, the clamp level switching circuit generates a normal clamp potential V.sub.0. A clamping pulse generating circuit is responsive to an output from the frame synchronizing signal detecting circuit for generating a clamping pulse. A clamping circuit is responsive to the clamping pulse for clamping an analogue video signal at the clamp potentials V.sub.0, V.sub.+ or V.sub.- from the clamp level switching circuit.

REFERENCES:
patent: 3476875 (1969-11-01), Davis
patent: 4707730 (1987-11-01), Alard
Nikkei Electronics, Mar. 12, 1984, pp. 112-116.

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