Clamping circuit for a PLL tuning system

Telecommunications – Receiver or analog modulated signal frequency converter – Signal selection based on frequency

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Details

455260, 455264, 381 15, H04B 1116

Patent

active

049033298

ABSTRACT:
An AM Stereo receiver is described which includes an AGC having an output which indicates whether the received signal has significantly decreased in level and having a clamping circuit for controlling the voltage at the input of a VCO. The clamping circuit is further defined as having a window detector for sensing a change in the voltage at the input of the VCO according to a predetermined threshold; a selectable controller, responsive to the window detector, for adjusting the voltage at the input of the VCO; and a window reduction circuit, responsive to the output signal of the AGC, for altering the predetermined threshold to provide the controller with a more sensitive indication of a drift in the voltage at the input of the VCO. The receiver additionally includes a conventional locked loop driver for steering the VCO according to the phase of the received input signal. When the AGC output signal indicates that the signal quality of the received signal has significantly decreased in level, or when the window detector indicates that the system is tuned outside of an established narrow "tuned" window, the locked loop driver is disabled to prevent the locked loop driver from introducing a beat note into the VCO.

REFERENCES:
patent: 4394778 (1983-07-01), Ikeguchi et al.
patent: 4406017 (1983-09-01), Takahashi
patent: 4476586 (1984-10-01), Tanaka et al.
patent: 4498191 (1985-02-01), Rogers
patent: 4523127 (1985-06-01), Sato
patent: 4568888 (1986-02-01), Kimura et al.
patent: 4680778 (1987-07-01), Krinock
patent: 4696056 (1987-09-01), Morita
"An Effective Method for Correcting the Loop Filter DC Drift of a PLL in the Out-of-Lock State Using a Phase Frequency Detector", IEEE 1986.

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