Clamping circuit and nonvolatile memory device using the same

Details Clamping circuit and nonvolatile memory device using the same Clamping circuit and nonvolatile memory device using the same

2002-12-23

2004-06-15

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250, C365S189060

Reexamination Certificate

active

06751126

ABSTRACT:

BACKGROUND OF THE INVENTION
1 Field of the Invention
The invention relates generally to a clamping circuit and a nonvolatile memory device using the same, and more particularly to a clamping circuit capable of improving the operating speed at a low operating voltage and electrical characteristics without using a manufacture process that allows the clamp circuit to operated at a low voltage.
2. Description of the Prior Art
In order to improve the level of integration and lower power consumption, a research and development on a circuit that operates at a low operating voltage has recently been actively made.
Meanwhile, if a voltage applied to the device is, increased as the level of integration in the device is increased, the device may be broken to cause defect. Thus, a clamping circuit for constantly supplying a voltage under which the device stably operates is required. In other words, the clamping circuit must supply a stable voltage under which the device properly operates regardless of the operation of the peripheral circuits or variation in the power supply voltage.
For example, a word line voltage and a bit line voltage (or drain voltage) are applied to the flash memory cell for a program operation or an erase operation. If the bit line voltage is applied high, the flash memory cell may be damaged. Thus, it is required that a constant voltage lower than the operating voltage must be stably applied to the bit line. To this end, the clamping circuit is employed.
A case where the bit line voltage is stably applied to the flash memory cell using the clamping circuit will be now explained.
FIG. 1
is a circuit diagram for explaining the clamping circuit and the nonvolatile memory device using the same according to the prior art.
Referring to
FIG. 1
, a typical nonvolatile memory device includes a main flash memory unit
110
, a reference flash memory unit
120
for generating a reference signal in order to verify a program state or an erase state of a selected flash memory cell C
111
of the main flash memory unit
110
, and a compare unit
130
having a compare means
131
for comparing the amount of current flowing into the flash memory cell C
111
of the main flash memory unit
110
and a reference flash memory cell C
121
of the reference flash memory unit
120
to determine data stored at the flash memory cell.
Of them, the main flash memory unit
110
includes a main flash memory cell array
111
having a plurality of operating flash memory cells (for convenience, only one flash memory cell shown), a first bit line select unit
112
for selecting one bit line BL of a plurality of bit lines (for convenience, only one bit line shown) like a Y address decoder, a first load unit
113
for supplying the power supply voltage (Vcc), and a first clamping circuit
114
for controlling the voltage applied from the first load unit
113
to the bit line node BL so that a stable voltage can be applied to the bit line node BL.
Meanwhile, the reference flash memory unit
120
includes a reference flash memory cell array
121
having a plurality of reference flash memory cells (for convenience, only one flash memory cell shown), a second bit line select unit
122
for selecting one bit line RBL of a plurality of bit lines (for convenience, only one bit line shown) like the Y address decoder, a second load unit
123
for supplying the power supply voltage (Vcc), and a second clamping circuit
124
for controlling the voltage applied from the second load unit
123
to the bit line node RBL so that a stable voltage can be applied to the bit line node RBL.
Further, the first clamping circuit
114
of the main flash memory unit
110
has a first NMOS transistor T
111
connected between the first load unit
113
and the bit line node BL, a PMOS transistor T
112
connected between the power supply voltage (Vcc) terminal and a gate electrode of the first transistor T
111
, for supplying charges to the gate electrode of the first NMOS transistor T
111
depending on the potential of the bit line node BL, and a second NMOS transistor T
113
connected between the gate electrode of the first transistor T
111
and a ground voltage (Vss) terminal, for discharging the charges from the gate electrode of the first NMOS transistor T
111
to the ground voltage (Vss) terminal depending on the potential of the bit line node BL. At this time, the PMOS transistor T
112
and the first and second NMOS transistors T
111
and T
113
operate as a variable resistor element the on resistance of which is changed depending on the voltage applied to the gates of the transistor T
112
, T
111
and T
113
. By controlling the voltage of the bit line node BL using the first clamping circuit
114
constructed above, the voltage of the bit line node BL can be applied to the main flash memory cell C
111
as a stable voltage under which the device properly operates.
Furthermore, the second clamping circuit
124
included in the reference flash memory unit
120
has the same structure as the first clamping circuit
114
included in the main flash memory unit
110
.
The operation of the nonvolatile memory device having the clamping circuit will be explained, wherein the operation of the clamping circuit
114
will be explained on the basis of the main flash memory unit
110
since the main flash memory unit
110
and the reference flash memory unit
120
have the same basic structure and operation.
At an initial state being a previous state that the nonvolatile memory device normally operates, the voltages of all the nodes including the bit line node BL are 0V. The voltage of 0V of the bit line node BL turns on the PMOS transistor T
112
in the clamping circuit
114
, which has the gate connected to the bit line node BL and turns off the second NMOS transistor T
113
. The power supply voltage (Vcc) is applied to the gate electrode of the first NMOS transistor T
111
through PMOS transistor T
112
of the ON state, so that the first NMOS transistor T
111
is turned on.
If the nonvolatile memory device starts to operate through the initial state, the power supply voltage (Vcc) is applied to the nonvolatile memory device through the first load unit
113
.
At this time, as the device is higher integrated, if the power supply voltage (for example, 1.6V) is applied to the flash memory cell C
111
intact, the cell C
111
may be damaged. In order to prevent this, the first clamping circuit
114
adjusts the voltage supplied from the first load unit
113
to be a voltage under which the device can stably operate (hereinafter called ‘operating voltage’) and then outputs the operating voltage to the bit line node BL, which will be described in more detail.
If the voltage supplied from the first load unit
113
is applied to the bit line node BL through the first NMOS transistor T
111
and the voltage of the bit line node BL becomes then higher than the operating voltage, the PMOS transistor T
112
becomes gradually close to the OFF state to have higher resistance value. The second NMOS transistor T
113
becomes gradually close to the ON state to have lower resistance value. Due to this, the amount of the charges supplied from the power voltage source to the gate electrode of the first NMOS transistor T
111
becomes higher than the amount of the charges discharged from the gate electrode of the first NMOS transistor T
111
to the ground voltage source. As the voltage applied to the second NMOS transistor T
113
is lowered, the voltage applied to the gate electrode of the first NMOS transistor T
111
is lowered. As a result, the resistance component of the first NMOS transistor T
111
is increased. As the resistance component of the first NMOS transistor T
111
is increased, the amount of current supplied to the bit line node BL is reduced. As the voltage applied to the first NMOS transistor T
111
is increased, the voltage supplied to the bit line node BL is lowered.
If the voltage of the bit line node BL is lowered than the operating voltage, the PMOS transistor T
112
becomes close to the ON state and the second NMOS transistor T
113
bec

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