Facsimile and static presentation processing – Facsimile – Specific signal processing circuitry
Patent
1990-06-25
1992-02-11
Groody, James J.
Facsimile and static presentation processing
Facsimile
Specific signal processing circuitry
358171, H04N 518, H04N 521
Patent
active
050879731
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to an image receiver control apparatus of a system transferring an image signal on which a clamp level reference signal and an amplitude reference signal are multiplexed.
BACKGROUND ART
Conventionally, a clamp level reference signal which is multiplexed with an image signal is used for detection of an amount of noise in addition to DC level restoration of the original image signal. A method of restoring a DC level is disclosed in the Japanese Unexamined Patent Publication JP-A-58-124373, for example. A method of performing the detection of the noise amount and control of a reproduction apparatus, by using the clamp level reference signal multiplexed with the image signal, is disclosed in the Japanese Unexamined Patent Publication JP-A-62-172879, for example. FIG. 1 shows an arrangement of a conventional image receiver control apparatus, in which the restoration of the DC level, the detection of the noise amount and automatic gain control are performed by using the above methods.
In FIG. 1, numeral 1 indicates an input signal, numeral 2 an analog clamper, numeral 3 an A/D converter and numeral 4 a digital output signal. The input signal 1 is clamped on a predetermined value by the analog clamper 2 and then the clamped signal is converted into, for example, an 8-bit digital signal by the A/D converter 3. A digital level comparator 5 determines a difference between a digital value obtained by A/D-converting a portion of the input signal corresponding to a clamp level reference signal and a predetermined digital value, e.g., a value "128". An integrator 6 integrates an output from the digital level comparator 5 and the integrated output is converted into an analog clamp level signal by a D/A converter 7. The analog clamp level signal is connected to the analog clamper 2 to form a feed-back loop, so that control is performed such that an average value of the digital values obtained by A/D-converting predetermined portions of the input signal is "128". Operation speeds of the digital level comparator 5 and the integrator 6 are the same as conversion speed of the A/D converter.
Numerals 8 to 17 indicates a circuit portion for detecting the noise amount. The values obtained by A/D-converting the clamp level reference signal ought to be substantially constant unless the noise is introduced. However, the values are usually different per each sample because of influence of noise on a transmission path. A variance of the sample values from the average value represents energy of the noise. Since generation of noise is a random process, it is necessary to use, as the noise level, a value obtained by processing on many sample values and a low pass filter processing in a time axis direction, i.e., a temporal filter processing to suppress their time variations. A difference between the sample values of the A/D-converted signal 4, one of which is delayed by one period of the same operation clock signal (to a terminal 19) as that of the A/D converter, is calculated by a flip-flop 8 and a subtracter 9. Then, the difference is sampled in a flip-flop 10 in response to the clock signal (b) supplied from a terminal 20. Next, a difference between the sampled values, one of which is delayed by one period of the clock signal (a) from a terminal 20, is determined by a flip-flop 11 and a subtracter 12. The timing when the clock signal (b) rises is during a period of the clamp level reference signal and indicates a timing of a signal used for noise detection. An absolute value of the difference is determined by a circuit indicated by numeral 13 and a signal corresponding to a noise level is obtained from the absolute value by a low pass filter in a time axis direction, i.e., a temporal filter 14. The temporal filter 14 is arranged as shown in FIG. 2 to suppress time variations of the input signal.
In FIG. 2, numeral 21 indicates a subtracter, numeral 22 an amplifier of gain K1, numeral 23 an adder, numeral 24 a delay circuit, and numeral 25 an amplifier of gain K2. A circuit portion con
REFERENCES:
patent: 4807034 (1989-02-01), Takeuchi et al.
patent: 4811087 (1989-03-01), Engel et al.
patent: 4833537 (1989-05-01), Takeuchi et al.
Groody James J.
Matsushita Electric - Industrial Co., Ltd.
Powell Mark R.
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