Clamp circuit to prevent ESD damage to an integrated circuit

Details Clamp circuit to prevent ESD damage to an integrated circuit Clamp circuit to prevent ESD damage to an integrated circuit

2000-03-11

2002-06-04

Nguyen, Matthew (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C257S357000

Reexamination Certificate

active

06400540

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable
REFERENCE TO MICROFICHE APPENDIX
Not Applicable
BACKGROUND OF THE INVENTION
The present invention relates to the field of electrical safety systems using on-chip protection elements to prevent damage to the device. More particularly, the present invention relates to circuits and devices for providing electrostatic discharge protection between power supply buses and the ground bus in a CMOS integrated circuit.
The accumulation of static electricity in the vicinity of an integrated circuit (IC) exposes the circuit to a potential failure in the form of an electrostatic discharge (ESD) event. This event refers to the phenomena in which the high static potential (ranging from hundred to thousand of volts) causes a discharge of current in excess of an ampere to flow between at least two external terminals of an integrated circuit. The ESD event current, if not properly handled within the integrated circuit, has the potential to disable or destroy the entire integrated circuit.
IC designs contain additional devices and circuits to handle the ESD event. These additional devices and circuits operate during an ESD event. When in the normal operating mode, the circuit terminals function at the normal design potential while either sending and receiving electrical signals from circuitry external to the IC or receiving power from circuitry external to the IC. The circuit network that conducts the ESD current, the ESD network, is required to conduct the ESD current and thereby reducing any potential damage to itself or to the remainder of the IC. The ESD damage to the IC must remain below detectable limits. It is highly desirable that the same ESD network causes negligible performance impact on the normal mode circuit function. As the ESD event is a fast transient event, the peak ESD event current flowing in the first few nanoseconds, the ESD network must conduct this fast transient current. During the normal mode of IC operation, the ESD network must not conduct any transient current.
To reduce the cost of implementing the ESD network, it is desirable to minimize the area of the IC used just for said network. As a result of this, where possible, the ESD network uses some IC devices and circuits that are also used during the normal operating mode of the IC. In CMOS, all the NMOS and PMOS transistors contain diodes between their sources and drains; and the particular well in which they are physically located. In the normal mode of operation, the proper external power is supplied to the IC and these diodes are biases between zero and some reverse bias resulting in a minimal current flow though the diodes. During an ESD event, power is not applied and these transistor diodes may be forward biased by the ESD event itself and conduct current accordingly.
In particular, CMOS output circuits or combination input-and-output circuits use a combination of large NMOS and large PMOS transistors. These large transistors, the output transistors, are connected to the IC external terminals. The drains of the output transistors form the cathode or the anode of large diodes wherein the opposite diode terminal is connected to the respective well of each output transistor. The n type well for the PMOS transistor is connected to VDD, the positive or power supply potential in the IC. The p type well for the NMOS transistor is connected to the ground potential in the IC. In the most commercially prevalent CMOS, all p type wells are connected together through additional p type material which results in all n type wells individually forming diode connections with the one p type material at ground potential. Some ICs use ESD networks which add additional diodes in parallel to the diodes that are an integral part of the output transistors. This practice improves the diode connectivity between the IC external terminals and the power buses internal to the IC.
During testing of an IC, the ESD event is caused to occur between pairs of the external terminals with the polarity of current applied one way and then a similar ESD event is applied with the external terminals reversed. As there are diodes between the external terminal pins and both the power and ground buses, the result of the applied ESD potential is that the ESD network routes the ESD current into the power and ground buses through the appropriate forward biased diodes. To complete the network and safely pass the ESD current through the network, the ESD current must pass between the power and ground bus. There are two possible polarities for the ESD current, both of which the ESD network must handle as a result of the reversal of the external terminals during ESD testing.
The most strenuous ESD event for the ESD network to handle is the situation in which the both external terminals used for the ESD testing are connected to output or input-and-output circuits. In other ESD test combinations, a least one external terminal is a power or ground terminal. These test conditions are less strenuous for the ESD network.
If in the ESD event the polarity of the event causes current to flow into the first terminal, that is the first terminal is at a more positive potential than the second terminal, the ESD event current is conducted readily from the first terminal to the power bus by means of the forward biased PMOS transistor drain inside the n type well connected to the power bus. Similarly, the ESD event current will flow out of the second terminal through the forward biased NMOS transistor drain inside the p type well connected to the ground bus. The ESD event current must also flow between the power bus and the ground bus to complete the current conduction loop from the first terminal to the second terminal thereby passing the ESD current safely through the IC and avoiding damage to the IC.
In normal operation the power supply potential is greater than the ground potential and a minimal current flows between the n type wells and the p type wells. Without additional devices and circuits in the ESD network, the ESD event current only passes from the power bus to ground bus by means of AC current, that current which is proportional to the product of the rate of change of the difference of the power and ground bus potentials; and the capacitance between buses. In some IC designs, the capacitance between the power and ground that exists between the p type wells and n type wells together with the rapid change in the relative bus potentials caused by the ESD event provides sufficient ESD current flow to protect the IC from damage. If insufficient capacitance is unavailable or cannot be feasibly added to the IC, the ESD network conducts the current from the power bus to the ground bus by an appropriate collection of devices and circuits, the ESD power to ground clamp, also called an ESD power to ground shunt. The ESD clamp must conduct the ESD event current while not being damaged by the event, not conducting current during the normal operation of the IC, and not being physically large as to adversely affect the cost of the IC.
A variety of clamp circuits have been used with ICs. These clamps consist of a primary device to carry the current and a control circuit to condition the primary conduction device to conduct during an ESD event, but not conduct under normal IC operation. The primary conduction devices that have previously been used in CMOS ICs are the NMOS transistor, the PMOS transistor, and a special device called a silicon controlled rectifier (SCR). Puar in U.S. Pat. No. 5,287,241 describes an ESD network using a PMOS clamping circuit. Dabral in the 1994 EOS/ESD Symposium Proceedings describes and NMOS clamping circuit. Ker in U.S. Pat. No. 6,011,681 used an SCR clamp. Each of these primary conduction devices has their respect advantages and disadvantages. The NMOS transistor has a high conductivity, but is itself susceptible to damage by the ESD event. The PMOS transistor is more rugged than the NMOS type, but the PMOS is less tha

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