Coded data generation or conversion – Analog to or from digital conversion – Nonlinear
Reexamination Certificate
2001-11-13
2003-02-04
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Nonlinear
Reexamination Certificate
active
06515602
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing system, and more particularly, to a clamp circuit and method which are capable of increasing the dynamic range of an input image signal and minimizing line noise.
2. Description of the Related Art
In general, image signals provided by an image signal source such as a video cassette recorder (VCR) or a charge coupled device (CCD) are almost analog signals. A video decoder that receives an analog image signal converts the analog image signal into a digital signal so as to be processed by the digital processor.
In devices that create the analog image signals, the direct current levels of the output image signals vary according to circuit driving methods and characteristics, in many cases. Therefore, when the image signals having different direct current levels are directly connected to a variable gain amplifier or an analog-to-digital converter (ADC) inside the video decoder, the image signals may be severely distorted or may mis-operate. In order to solve this problem, a method of uniformly adjusting the direct current level of the image signal using a clamp circuit has been developed.
FIG. 1
shows a conventional clamp circuit. The clamp circuit includes a variable gain amplifier (VGA)
10
, a clamp unit
12
, an analog-to-digital converter (ADC)
14
, and a clamp controller
16
. The VGA
10
amplifies the direct current level of an analog input signal A_IN by a predetermined gain and outputs the amplified signal. The clamp unit
12
clamps the direct current level of the analog signal whose gain is amplified to a predetermined level in response to a clamp pulse output from the clamp controller
16
. The ADC
14
converts the clamped analog signal into the digital signal and generates digital data D_OUT. The clamp controller
16
compares the digital data D_OUT output from the ADC
14
with a digital code value that as a reference and generates a control signal for controlling the clamp unit
12
in response to the comparison result.
Since the conventional clamp circuit shown in
FIG. 1
performs clamping without removing the offset component generated by the VGA
10
, the dynamic range of an input signal can be reduced. However, in the case of an image processing system having a large gain such as a camcorder, clamping must be performed such that the offset that can be generated in an entire image processing path can be removed. Therefore, it is required that the dynamic range of the input signal is set to be wide.
FIG. 2
shows another circuit illustrating a conventional clamp circuit. The circuit includes a clamp unit
20
, a variable gain amplifier (VGA)
22
, an ADC
24
, and a clamp controller
26
. The circuit shown in
FIG. 2
is different from the circuit shown in
FIG. 1
in that the gain is amplified after the clamp unit
20
clamps the input signal A_IN. In such a case, since the offset shown in the VGA
22
can be removed by the clamp unit
20
, the problem in that the dynamic range of the input signal is reduced can be solved. However, even when the level clamped by the clamp unit
20
is small, the clamped level can be amplified by the VGA
22
. Therefore, in the case of a video system, in which clamping is performed for every horizontal line, line noise can appear in parts of an image having high gains.
An effective clamping method which is capable of compensating for defects shown in the clamp circuit shown in FIG.
1
and the clamp circuit shown in
FIG. 2
is required.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a clamp circuit which is capable of minimizing line noise according to the change in the gain of an image signal and increasing the dynamic range of an input signal.
It is another object of the present invention to provide a clamp method which is performed by the clamp circuit.
The first object is achieved by the clamp circuit having a first clamp unit, a variable gain amplifier, a second clamp unit and a clamp controller. The first clamp unit operates under a first set of conditions, clamps the reference input section of an analog image signal according to at least one first clamp pulse and fixes the DC bias level of the image signal to a predetermined level. The variable gain amplifier (VGA) amplifies the gain of an image signal clamped by the first clamp unit and outputs the signal whose gain is amplified. The second clamp unit operates under a second set of conditions, clamps the reference input section of an image signal whose gain is amplified according to at least one second clamp pulse and adjusts the DC bias level. The analog-to-digital converter (ADC) converts either the output of the variable gain amplifier or the image signal clamped by the second clamp unit into a digital signal and outputs the converted signal as predetermined digital data. The clamp controller obtains an average value by accumulating the digital data and generates the first clamp pulse and the second clamp pulse by comparing the obtained average value with a target level.
In one embodiment, the first clamp unit adjusts a digital code value using the first clamp pulse, converts the digital code value into an analog signal and adjusts the DC bias level using the converted signal. The second clamp unit can adjust the DC bias level by selectively sourcing and sinking predetermined current in accordance with the second clamp pulse. The first clamp pulse can include a first up signal and a first down signal, and the second clamp pulse can include a second up signal and a second down signal. The clamp controller can include a clamp selection circuit, a first clamp pulse generator and a second clamp pulse generator. The clamp selection circuit generates first and second enable signals for selecting the first clamp unit and the second clamp unit in response to a start signal applied under the first set of conditions and a horizontal synchronization signal. The first clamp pulse generator accumulates the digital data in response to the first enable signal, the horizontal synchronization signal and a predetermined clock signal. The first clamp pulse generator obtains the average value of the accumulated data, compares the average value with a first target level and outputs the comparison result as the first up signal or the first down signal. The second clamp pulse generator accumulates the digital data in response to the second enable signal, the horizontal synchronization signal and the clock signal. The second clamp pulse generator obtains the average value of the accumulated data, compares the average value with a second target level and outputs the comparison result as the second up signal or the second down signal.
In one embodiment, one of the first set of conditions is that supplied voltage is applied at an initial stage. One of the first set of conditions can also be that the gain of the input image signal is adjusted.
In one embodiment, each of the first and second clamp pulse generators includes an accumulator, a comparator and an up/down signal generator. The accumulator accumulates the digital data of the reference input section in response to a predetermined accumulation clock signal, obtains the average value of the accumulated data and outputs the obtained average value. The comparator compares the average value with one of the first and second target levels and outputs the comparison result. The up/down signal generator outputs the output value of the comparator as one of the first/second up signal and the first/second down signal in response to a predetermined comparison clock signal. The accumulator can include a first latch, an adder and a second latch. The first latch latches the digital data output from the ADC in response to a reset signal and the accumulation clock signal and outputs the latched data. The adder adds data output from the first latch to a previous digital data value and outputs the addition result. The second latch latches the output signal of the adder in response to the re
Ahn Gil-cho
Jung Jae-cheun
Mills & Onello LLP
Young Brian
LandOfFree
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