Clamp circuit

Details Clamp circuit Clamp circuit

1999-03-15

2001-05-08

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S323000, C327S330000, C348S707000

Reexamination Certificate

active

06229371

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clamp circuit, and more particularly, to a clamp circuit for video signal processing and or the like.
2. Description of the Related Art
First, the reason why a clamp circuit is necessary for video signal processing will be explained.
FIGS. 6A
to
6
C illustrate the relationship between a video signal and pedestal level. When the pedestal level
101
is constant as shown in
FIG. 6B
, the white level portion of the video signal
103
is displayed in white on the screen and the black level portion is displayed in black on the screen as shown in FIG.
6
A.
If the signal is input by means of a CR (capacitance-resistance) coupling, the direct-current component is lost as shown in FIG.
6
C. As a result, what should be white does not become white, resulting in an image of wrong contrast. Thus, it is necessary to provide a direct-current restorer to make the pedestal level
101
constant forcefully.
The pedestal clamp circuit for making the pedestal level
101
constant is a circuit which matches the black level
102
determined externally to the black level contained in the video signal
103
.
Next, the relationship between the video signal waveform in gray scale which contains a sync signal and its voltage level will be described as a reference.
FIG. 7
is a waveform diagram illustrating the relationship between the video signal waveform in gray scale which contains a sync signal and its voltage level.
If there is no sync pulse, it is sufficient to forcefully level-shift the lowest voltage inputted, to the black level provided externally.
If there is a sync pulse, it is necessary to first tune the lowest voltage inputted, to the reference potential provided externally, in order to detect this sync pulse.
Now a basic clamp circuit will be described.
FIG. 8
is a circuit diagram of a conventional level clamp circuit, and
FIG. 9
is a diagram showing input and output waveforms of this level clamp circuit.
FIG. 8
shows a basic system of a circuit configuration where a preset potential equals the lowest potential inputted. Such a circuit is also called a DC insertion circuit.
This level clamp circuit consists of a capacitor C, diode Di, and DC power supply (with a preset voltage Vr), wherein an input voltage Vin is input to the input side of the capacitor C and an output voltage Vout is output from the output side of the capacitor C.
The circuit configuration is such that the preset voltage Vr is clamped to the lowest voltage of the input voltage Vin. In steady state, the diode Di remains off.
Actually, however, it is clamped to a level (see
FIG. 9
) &Dgr;VF lower than the lowest voltage where the diode Di does not turn on.
This &Dgr;VF depends on the backward resistance (rb) of the diode Di, load resistance (not shown) to be connected to the output terminal Vout, forward resistance (rf) of the diode Di, etc.
Specifically, it is given by the following equation:
&Dgr;
VF
/(
Vin−&Dgr;VF
)=
rf/rb
  (1)
As can be seen from
FIGS. 8 and 9
, setting the desired voltage to Vr allows it to be clamped to a constant potential regardless of the duty of input waveforms.
The disadvantage of this circuit is that it is impossible to set a clamp level precisely: there is an error voltage of &Dgr;VF with respect to Vr.
Now another conventional circuit of this type will be described.
FIG. 10
is a circuit diagram of another conventional level clamp circuit. This circuit uses an operational amplifier.
The basic form of clamp circuits described earlier cannot clamp voltage accurately. To correct this situation, clamp circuits such as the one shown in
FIG. 10
reduce the error in clamp voltage by inserting a diode (actually, the emitter and base of the transistor Q
1
in this example) in the feedback loop
104
.
Referring to
FIG. 10
, the clamp circuit utilizing a conventional operational amplifier consists of an operational amplifier A
11
which has a black level voltage VBL applied to its non-inverting input terminal
105
, a capacitor C
1
which has one end connected to the inverting input terminal
106
of the operational amplifier A
11
and the other end inputted a video signal
103
, an NPN transistor Q
1
whose base is connected to the output terminal
107
of the operational amplifier A
11
and whose emitter is connected to the inverting input terminal
106
of the operational amplifier A
11
and whose collector is connected to the power supply VCC, and a constant current source I
1
connected between the emitter of the NPN transistor Q
1
and ground. Also, an output terminal Vout is connected to the emitter of the NPN transistor Q
1
.
Since the emitter of the NPN transistor Q
1
is connected to the inverting input terminal
106
of the operational amplifier A
11
, this clamp circuit results in an amplifier which generally has negative feedback. This works to equalize the voltage at the emitter (i.e., output terminal Vout) of the NPN transistor Q
1
to the black level voltage VBL.
Specifically, the NPN transistor Q
1
and constant current source I
1
replace the difference between the pedestal voltage and black level voltage VBL of the video signal
103
with the voltage across the capacitor C
1
by charging and discharging the capacitor C
1
, to equalize the pedestal voltage of the video signal
103
obtained at the emitter of the NPN transistor Q
1
to the black level voltage VBL.
FIG. 11
is a waveform diagram representing the input-output characteristics of the clamp circuit. As shown in the figure, the ground (GND) potential of the video input signal
103
is level-shifted, in the output signal Vout, to the black level potential (VBL).
Incidentally, a circuit equivalent to this clamp circuit is disclosed in Japanese Patent Application Laid-Open No. 5-83595 (see
FIG. 7
of Application No. 5-83595, in particular).
The differential amplifier
61
, transistor
21
, transistor
22
and resistor
34
, and capacitor
42
disclosed in
FIG. 7
of above-mentioned Application No. 5-83595 correspond the operational amplifier A
11
, transistor Q
1
, constant current source I
1
, and capacitor C
1
in the example of conventional circuit (
FIG. 10
) herein, respectively. Also, the voltage source
71
in
FIG. 7
of above-mentioned Application No. 5-83595 corresponds to the black level voltage VBL in the example of conventional circuit (
FIG. 10
) herein.
Other examples of clamp circuits employing operational amplifiers of this type are disclosed in Japanese Patent Application Laid-Open Nos. 62-164380, No. 8-204994, and No. 3-127559.
Besides, as examples of other clamp circuits, Japanese Patent Application Laid-Open No. 63-283278 discloses a clamp circuit which corrects line level variations by feeding back its output to an inverting input terminal and using the feedback loop as an integrator with a switchable filter inserted in the feedback loop. Japanese Patent Application Laid-Open No. 3-175795 discloses a feedback clamp system which shortens the time required for a feedback loop to stabilize, by feeding back the output of a clamp circuit to the input of the clamp circuit via an error detection circuit and then temporarily opening the feedback loop in initial states such as at power-on and bringing, instead, the reference voltage of the clamp circuit close to a set point. Japanese Patent Application Laid-Open No. 3-258116 discloses a gain control circuit which corrects variations in the signal level of input signals in a stable and reliable manner by comprising a feedback loop for feeding back the output of a clamp circuit to the input side of the clamp circuit through an A/D (analog-digital) converter and clamp level control circuit, as well as a feedback loop for feeding back the output of the A/D converter to the input side of the A/D converter through an amplitude control circuit, and by giving priority to the operation of the clamp level control circuit over the operation of the amplitude control circuit. Japanese Patent Application Laid-Open No. 4-314270 discloses a clamp circui

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