Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-10-13
2004-01-13
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S718000, C257S675000, C257S722000
Reexamination Certificate
active
06677662
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to wire bonding a semiconductor package and, more particularly but not by way of limitation, to a clamp and a heat block of the wire bonding of a semiconductor package, with which the wire bonding can be easily and safely conducted.
2. History of Related Art
It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal lead frames for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the lead frame are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
As set forth above, the semiconductor package therein described incorporates a lead frame as the central supporting structure of such a package. A portion of the lead frame completely surrounded by the plastic encapsulant is internal to the package. Portions of the lead frame extend internally from the package and are then used to connect the package externally. More information relative to lead frame technology may be found in Chapter 8 of the book
Micro Electronics Packaging Handbook
, (1989), edited by R. Tummala and E. Rymaszewski, and incorporated by reference. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.
Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1×1 mm to 10×10 mm. A typical semiconductor package is a leadframe having a plurality of tie bars internally extended from the corners over the frame body, a chip paddle in contact with the tie bars on which a semiconductor chip is later mounted, a plurality of internal leads regularly formed at a distance away from and along the perimeter of the chip paddle, external leads which are extended from the internal leads having terminals being connected to the frame body, and dam bars which are positioned between the internal leads and the external leads connected to the frame body. Half-etched parts are provided to the sides of the chip paddle, to the chip paddle facing the ends of the internal leads, and to the tie bars regions near the chip paddle.
After a semiconductor chip is bonded onto the chip paddle via an adhesive, a clamp is placed on the upper surface of the internal leads in a leadframe and then a heat block guided by a guide block is allowed to underlay the entire bottom surface area of the chip paddle and the internal leads to fix or support the chip paddle, the semiconductor chip and the internal leads. The clamp, in combination with the heat block and guide block, prevents the internal leads from being changed and positioned during a wire bonding process.
Next, an electrical connection is formed with conductive wires, such as gold wires or aluminum wires, between the bond pads of the semiconductor chip and the internal leads of the leadframe. The semiconductor chip, the conductive wires, the chip paddle, the tie bars, and the internal leads are next encapsulated by an encapsulate to form a package body. The half-etched section of the internal leads, being individually unsupported, tend to warp downwardly, causing a bonding defect. This results in a lower production yield.
In addition, a groove in the heat block, which is guided by a protrusion on a guide block, is relatively narrow. The result is a reduction in the supporting area of the guide block and tilting of the leadframe. Thus, the wire bonding process cannot be accurately implemented.
Typically, a mark for indicating the first of a plurality of internal leads is provided. Using this mark, the wire bonding process is conducted with the aid of a predetermined program. However, the mark for indicating the first internal lead is frequently screened by the clamp, thereby making it difficult to conduct the wire bonding process.
BRIEF SUMMARY OF THE INVENTION
In one embodiment of the present invention, there is provided a semiconductor chip having an upper surface and a bottom surface. A plurality of input bond pads and output bond pads on the upper surface of the semiconductor chip and along the circumference of the semiconductor chip are electrically connected to the semiconductor chip.
A leadframe is provided having a plurality of tie bars. Each of the tie bars has a side surface and a bottom surface. The plurality of tie bars are connected to the corners of a chip paddle. The plurality of the tie bars externally extend from the chip paddle and have a half-etched section. A plurality of dam bars are provided on the leadframe to help limit flow of encapsulation material on the leadframe.
A plurality of internal leads connect to the leadframe. Each of the leads has a side surface and a bottom surface. The leads are formed at regular intervals along and spaced apart from the perimeter to the chip paddle and extend towards the chip paddle.
A chip paddle is provided which has a top surface, a side surface and a bottom surface. The chip paddle is bonded to the bottom surface of the semiconductor chip by an adhesive. The chip paddle has corners, a perimeter and a half-etched section at the lower edge of the chip paddle along the chip paddle perimeter.
A plurality of conductive wires are electrically connected to and located between the plurality of internal leads and the semiconductor chip. Encapsulating material encapsulates the semiconductor chip, conductive wires, chip paddle, and the leads to form a package body. The flow of the encapsulation material is limited by the dam bars formed on the leadframe. The dam bars also serve to stabilize the leads on the leadframe. After encapsulation, the chip paddle, leads, and tie bars are externally exposed at respective side and bottom surfaces. There is provided a heat block which has a pedestal on its upper surface. The pedestal serves to firmly support the half-etched section of the internal leads and maintain the internal leads in a fixed position during the wire bonding process. The heat block serves to protect the semiconductor chip from excessive heat during the wire bonding process.
In another embodiment of the present invention, there is provided a second heat block assembly having a heat block, which has at its bottom surface a groove similar to a raised section formed at an upper surface of a guide block. The groove and raised section meet when the heat block is guided by the guide block. Du
Chung Young Suk
Park Soo Jung
Amkor Technology Inc.
Rose Kiesha
Stetina Brunda Garred & Brucker
Zarabian Amir
LandOfFree
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