CISFET Processing including simultaneous implantation of spaced

Details CISFET Processing including simultaneous implantation of spaced CISFET Processing including simultaneous implantation of spaced

1978-11-20

1980-07-01

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

148187, 357 23, 357 40, 357 59, 357 91, H01L 734, H01L 1100, B01J 1700

Patent

active

042104653

ABSTRACT:
A process for forming a CIS (conductor-insulator-semiconductor) integrated circuit having one or more non-memory field-effect transistors, and one or more polysilicon resistors and/or polysilicon conductors. A single mask and implant sequence is used to establish the threshold voltage of the field-effect transistor and the resistance (conductance) of the polysilicon components. The polysilicon components are formed to predetermined sizes, as needed, so that the threshold-determining implant provides the desired polysilicon resistance value(s).

REFERENCES:
patent: 3841926 (1974-10-01), Garnache et al.
patent: 3889358 (1971-06-01), Bierhenke
patent: 3891190 (1975-06-01), Vadasz
patent: 3996657 (1976-12-01), Simko
patent: 4011105 (1977-03-01), Paivinen et al.
patent: 4019197 (1977-04-01), Lohstroh et al.
patent: 4075045 (1978-02-01), Rideout
patent: 4080718 (1978-03-01), Richman
patent: 4080719 (1978-03-01), Wilting
patent: 4099317 (1978-07-01), Su
patent: 4102733 (1978-07-01), De La Moneda et al.

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