Circular access linkage loop configuration for system communicat

Details Circular access linkage loop configuration for system communicat Circular access linkage loop configuration for system communicat

1981-01-12

1983-05-10

Brigance, Gerald L.

Multiplex communications

Wide area network

Packet switching

370 88, H04J 302

Patent

active

043833144

ABSTRACT:
A plurality of CML integrated circuit chips with input and output gates connected in a circular access linkage loop output-to-input with each chip having an interface mechanism comprising an interface register and a bypass arrangement between the input gate and the output gate so that information may flow from a transmitter output gate to a receiver input gate uni-directionally, (clockwise or counter-clockwise) through the loop by means of the bypass with minimal delay.
Utilizing this circular access linkage loop together with a junction box, a number of access loops can be joined together to increase the number of chips which can be linked together.
Also disclosed is a multiplexing scheme utilizing the circular access linkage loop for increasing the gate per pin ratio and for higher speed communication between chips.

REFERENCES:
patent: Re28811 (1976-05-01), Pierce
patent: 3600519 (1971-08-01), McNeilly
patent: 3732543 (1973-05-01), Rocher et al.
patent: 3740483 (1973-06-01), Pedersen
patent: 3786419 (1974-01-01), Nick
patent: 3890471 (1975-06-01), Hachenburg
patent: 4002842 (1977-01-01), Meyr et al.
patent: 4011412 (1977-03-01), Mattern
patent: 4039757 (1977-08-01), Frisone
patent: 4205326 (1980-05-01), Porter et al.
patent: 4334305 (1982-06-01), Girardi

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