Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-08-22
2008-10-07
Dinh, Son (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
Reexamination Certificate
active
07433262
ABSTRACT:
A method for delaying a control signal, includes receiving a clock signal, determining a number of delay elements required to generate a first delay equal to a target amount of the period of the clock signal, receiving a data signal having an edge generated at the same time as an edge of the control signal, determining a fraction number equal to the number of delay elements needed to generate a second delay for the data signal or the control signal to align their edges, divided by the number of cascaded delay elements necessary to provide a delay equal to the target amount of the period of the clock signal, multiplied by the number of delay elements to generate the first delay, and delaying the control signal by the number of cascaded delay elements to realize said first delay altered by the fraction number of delay elements.
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Matulik Eric
Schumacher Frederic
Vergnes Alain
Atmel Corporation
Byrne Harry W
Dinh Son
Schwegman Lundberg & Woessner, P.A.
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