Circuits, systems, and methods with a memory interface for augme

Details Circuits, systems, and methods with a memory interface for augme Circuits, systems, and methods with a memory interface for augme

1998-09-17

1999-12-14

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365191, 395834, G11C 800

Patent

active

060026324

ABSTRACT:
A digital computing system (30). The digital computing system includes a memory (36) and a memory controller (34). The memory comprises at least one memory bank (B0), and that bank comprises a plurality of rows (R.sub.0 -R.sub.N) and a plurality of columns (C.sub.0 -C.sub.N). The memory controller circuit is coupled to control the memory, and comprises a first bus (38) for providing an address to the memory, and three additional buses (38, 40). A first of these additional buses provides a row address strobe signal (RAS*) to the memory, where assertion of the row address strobe signal represents an indication that an address on the bus is a valid row address directed to one of the plurality of rows. A second of these additional buses provides a column address strobe signal (CAS*) to the memory, where assertion of the column address strobe signal represents an indication that an address on the bus is a valid column address directed to at least one of the plurality of columns. A third of these additional buses provides a bank close signal (BC*) to the memory, where assertion of the bank close signal represents a request to the memory to immediately de-activate an active one of the plurality of rows.

REFERENCES:
patent: 5701438 (1997-12-01), Bains
patent: 5802395 (1998-09-01), Connolly et al.

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