Pulse or digital communications – Synchronizers
Reexamination Certificate
1999-09-28
2003-02-11
Corrielus, Jean (Department: 2631)
Pulse or digital communications
Synchronizers
C327S141000, C326S093000
Reexamination Certificate
active
06519301
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to digital data circuits, and are more particularly directed to systems requiring the passage of information between different clock domains.
Digital systems often include circuits operating at different clock rates, and often there is a need to communicate information between such circuits while accommodating the accompanying change in clock rate between the circuits. Such information may include one or more bits in the form of control signals, flags, or other state indicators. In any event, the bit(s) cannot be directly communicated between circuits operating at different clock speeds due to potential metastability problems. By way of further explanation, such metastability problems may occur because if a circuit operating a first clock speed attempts to sample a bit state from a circuit operating at a second clock speed, there is the possibility that the sampled bit state may change at the instant it is being sampled. If this occurs, the resulting sample may be unstable, possibly fluctuating between low and high before settling on one of the values in a non-deterministic manner. Indeed, the resulting sample also may take on a value that is neither a digital high (e.g., 1) nor a digital low (e.g., 0) which is clearly an undesirable and problematic result. Lastly, note that the preceding discussion regarding passing information across different clock speeds also applies in general to circuits operating at the same clock speeds, but where the circuits are asynchronous with respect to one another. In other words, in this instance, a data bit cannot be directly passed from one circuit to another asynchronously operating circuit without the risk of an erroneous or invalid sampling of that bit. Given the two different scenarios now provided (i.e., different clock speeds or same but asynchronous clock speeds), and for purposes of definition for the remainder of this document, both may be collectively referred to as examples of crossing clock domains. In other words, both examples demonstrate a first circuit operating in a first clock domain and passing information to a second circuit operating in a second and different clock domain.
By way of further background,
FIG. 1
illustrates a block diagram of a prior art system
10
which addresses the cross-domain issues raised above, and more particularly system
10
illustrates an example where different clock speeds are used by different circuits and information is communicated between those circuits. System
10
includes two state machines and, for sake of reference, a first is shown as state machine A while a second is shown as state machine B. Each of state machines A and B is clocked according to a respective clock signal CLK
A
and CLK
B
, where these clock signals are at different speeds. As an example, assume that CLK
A
equals 25 MHz while CLK
B
equals 100 MHz. Accordingly, and as detailed below, system
10
represents an example of two circuits, which are illustrated by way of example as state machines, where it is desired for request information to be communicated between those circuits. For reasons detailed later, the passage of such information in the prior art requires a first communication path from state machine A to state machine B, and a second communication path from state machine B to state machine A. Each of these paths is described separately, below.
Looking to the path of communication from state machine A to state machine B, state machine A has a SET control signal and a CLEAR control signal coupled to a flag F
1
. Flag F
1
may represent various types of information, where for the present example assume that flag F
1
is a one-bit indicator from state machine A that, in response to a setting of the flag, state machine B is to take some action. The action of state machine B may be completely unrelated to state machine A or, alternatively, it may related to state machine A (e.g., such as state machine B taking action with respect to data, where the data also relates in some manner to state machine A). The state of flag F
1
is connected to an input of a synchronizer S
AB
, and the output of synchronizer S
AB
is connected to state machine B. Synchronizer S
AB
is constructed such that its input is connected to the data input of a latch L
AB1
, and the output of latch L
AB1
is connected to the data input of a latch L
AB2
. The output of latch L
AB2
provides the output of synchronizer S
AB
and, thus, as stated above, is connected to state machine B. Lastly, both of latches L
AB1
and L
AB2
are docked by CLK
B
.
Looking to the path of communication from state machine B to state machine A, note that state machine B is also operable to provide a one-bit CONFIRM control signal to state machine A via a synchronizer S
BA
where the functionality of the CONFIRM signal is described later. More particularly with respect to the CONFIRM signal, it is connected to the input of a synchronizer S
BA
, and the output of synchronizer S
BA
is connected to state machine A. Synchronizer S
BA
is constructed such that its input is connected to the data input of a latch L
BA1
, and the output of latch L
BA1
is connected to the data input of a latch L
BA2
. The output of latch L
BA2
provides the output of synchronizer S
BA
and, thus, as stated above, is connected to state machine A. Lastly, both of latches L
BA1
and L
BA2
are clocked by CLK
A
.
The operation of system
10
is now described, with particular emphasis on the notion of communicating information across clock domains from state machine A to state machine B. By way of example, assume that the cross-domain information is the state of flag F
1
. Further, when the state of flag F
1
is changed by state machine A, the change ultimately is detected by state machine B so that in response to that change state machine B may take a corresponding action. Thus, assume at a given time that state machine A is ready to request an action of state machine B. At this time, state machine A indicates this status by asserting its SET control signal and thereby setting flag F
1
. At the first assertion of CLK
B
following the setting of flag F
1
, latch L
AB1
latches the set flag. At the second assertion of CLK
B
following this assertion of SET, latch L
AB2
latches the set flag F
1
from latch L
AB1
, and thereby provides it to state machine B. Note, therefore, that communication of the set flag consumes two CLK
B
periods. Next, and in response to the set flag F
1
, state machine B takes the necessary action in response to the set flag F
1
.
After state machine B has taken its action, state machine B is required to acknowledge to state machine A that state machine B has responded to the set flag F
1
. Accordingly, state machine B provides such an acknowledgment via its CONFIRM signal and through synchronizer S
BA
. More particularly, state machine B asserts the CONFIRM signal and, at the first assertion of CLK
A
following the assertion of the CONFIRM signal, latch L
BA1
latches the asserted CONFIRM signal. At the second assertion of CLK
A
following the assertion of the CONFIRM signal, latch L
BA2
latches the asserted CONFIRM signal, and thereby provides it to state machine A. Further with respect to this communication, however, note the required use of clock cycles in this regard. Specifically, recall that synchronizer S
BA
is clocked by CLK
A
and, hence, at 25 MHz. Thus, when state machine B asserts the CONFIRM signal, it cannot assert it only for one period of CLK
B
because, in that case, there is a chance that CLK
A
will not transition during that one period of CLK
B
and, if this failure occurs, then the asserted CONFIRM signal will not be latched by latch L
BA1
. Indeed, given the example speeds of CLK
A
equal to 25 MHz and CLK
B
equal to 100 MHz, one skilled in the art should appreciate that to ensure proper latching of the CONFIRM signal state machine B must maintain its ass
Brady III W. James
Corrielus Jean
Hernandez Pedro P.
Telecky , Jr. Frederick J.
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