Circuits, systems and methods for memory mapping and display con

Computer graphics processing and selective visual display system – Display driving control circuitry – Controlling the condition of display elements

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G09G 500

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active

060258403

ABSTRACT:
A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.

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