Circuits, systems and methods for memory mapping and display con

Details Circuits, systems and methods for memory mapping and display con Circuits, systems and methods for memory mapping and display con

1998-04-24

2000-09-12

Chauhan, Ulka J.

Computer graphics processing and selective visual display system

Computer graphic processing system

Interface

345515, 711202, 711217, G06F 1314, G09G 536

Patent

active

061184616

ABSTRACT:
A processing system 100 is disclosed which includes a system master 101, a system bus 102 coupled to the master, and a plurality of bus interface circuits 106 coupled to bus 102. A first one of the bus interfaces 106 includes a mapping signal input coupled to the master and a mapping signal output, the first bus interface 106 operable to latch-in at least one first selected address bit presented by the master on the system bus in response to a mapping enable signal received at the mapping signal input from the master 101. A second bus interface 106 is provided coupled to the bus 102 and having a mapping signal input coupled to the mapping signal output of first bus interface 106, the second bus interface 106 operable to latch-in at least one second selected address bit presented by the master 101 on the bus 102 in response to a second mapping enable signal received at the mapping input of the second bus interface 106 from the first bus interface 106.

REFERENCES:
patent: 5473573 (1995-12-01), Rao
patent: 5745786 (1998-04-01), Juall
patent: 5748982 (1998-05-01), Smith et al.
patent: 5778196 (1998-07-01), Chen
patent: 5797036 (1998-08-01), Kikinis
patent: 5928343 (1999-07-01), Farmwald et al.
patent: 5956522 (1999-09-01), Bertone et al.

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