Multiplex communications – Communication over free space – Combining or distributing information via time channels
Reexamination Certificate
1997-12-10
2001-12-18
Yao, Kwang B. (Department: 2664)
Multiplex communications
Communication over free space
Combining or distributing information via time channels
C370S513000
Reexamination Certificate
active
06331976
ABSTRACT:
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to data communications, and are more particularly directed to circuits, systems, and methods for synchronization word detection in bitstream communications apparatus. By way of example, therefore, the background and embodiments are discussed below in the context of time division multiple access (“TDMA”) apparatus.
TDMA bitstream systems are typically implemented in the context of wireless communications, and also may exist in other environments where it is desirable to communicate a common bitstream to various receivers where each receiver is able to distinguish information intended for it versus information intended for a different receiver. In this regard and as detailed later, a TDMA bitstream includes packets of information. Each information packet generally includes user data which is preceded in the packet by what is referred to in this document as a synchronization word. The synchronization word is a bit pattern known to each receiver. Thus, a receiver may detect the synchronization word as a basis for defining the boundaries of other information in the packet. More specifically, typically following the synchronization word is a receiver identifier, which itself is followed by user data intended for the identified receiver. Consequently, by detecting the synchronization word, the receiver may then determine the boundary of the synchronization word itself. Typical systems detect the synchronization word after having received a portion, but not all, of the synchronization word. Thus, once a sufficient portion of the synchronization word has been received and determined to be a part of the synchronization word, the receiver may then determine the end of the synchronization word and thereby define the beginning and end of the other information within the packet (i.e., the receiver identifier and the user data).
Given the above, one skilled in the art will appreciate the need to accurately and efficiently identify the synchronization word in TDMA communications. Accuracy in detecting the synchronization word is critical because a failure to identify the synchronization word will cause a failure of communication with respect to the remainder of the information packet. Efficiency in detecting the synchronization word manifests itself in various manners. For example, one factor affecting the ability to detect the synchronization word is based on the power of the transmitted signal. In this regard, a higher power output provides a larger amplitude in transmitted signal. This increased amplitude may be used to overcome any noise in the signal, thereby improving the ability to properly detect the synchronization word by the receiver(s). However, as is common in electronic circuit implementation, an increased power requirement is often considered inefficient. Thus, efficiency suggests or may require reducing the power output signal while still obtaining a satisfactory probability of proper detection of the synchronization word. Another efficiency example arises in the timing of synchronization word detection. Particularly, note that an amount of elapsed time may be measured from the time the beginning of the synchronization word is received by a receiver and the time the receiver thereafter detects that the incoming information constitutes the synchronization word. If this elapsed time becomes too large, it may be considered a delay on the operation of the receiver. Such a delay also may be considered in evaluating the efficiency of the receiver. As yet another example, some prior art systems provide impressive levels of accuracy in synchronization word detection, but do so by requiring specific attributes of the signal to be known to the receiver. For example, one such system, as described below, requires that the receiver have access to the variance of the signal-to-noise ratio (“SNR”) of the incoming signal in order to identify an incoming synchronization word. This SNR variance may be difficult and complex to ascertain. Additionally, greater computational ability is likely to be required of the receiver to detect the incoming synchronization word even given the SNR variance. In some systems, therefore, these additional demands may be deemed inefficient given design or other criteria considered for the system.
In view of the above, there arises a need to address the drawbacks of the prior art. Thus, the inventive embodiments below contemplate such drawbacks and provide improved circuits, systems, and methods for synchronization word detection, such as in TDMA apparatus.
BRIEF SUMMARY OF THE INVENTION
In one embodiment, there is a communication system comprising circuitry for receiving a bitstream packet. The bitstream packet comprises at least three groups of bits: (1) a plurality of preamble prefix bits having a predetermined bit pattern; (2) a plurality of synchronization word bits following the plurality of preamble prefix bits; and (3) a plurality of data bits following the plurality of synchronization word bits. The system further includes circuitry for completing a carrier and clock recovery operation in response to receiving a first portion of the plurality of preamble prefix bits. Still further, the system includes circuitry for determining a location of the plurality of synchronization word bits within the bitstream packet. The circuitry for determining comprises circuitry for performing a number of comparisons between a bit test pattern vector and a sample vector of bits from the bitstream packet. The bit test pattern vector and the sample vector of bits both change for each of the number of comparisons. For at least one of the number of comparisons the sample vector of bits comprises a second portion of the plurality of preamble prefix bits following the first portion of the plurality of preamble prefix bits. Further, for at least some of the number of comparisons, the bit test pattern vector comprises one or more bits matching the predetermined bit pattern of the plurality of preamble prefix bits and further comprises one or more bits matching the synchronization word bits. Other circuits, systems, and methods are also disclosed and claimed.
REFERENCES:
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Brady III W. James
Hernandez Pedro P.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Yao Kwang B.
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