Circuits for reducing leakage currents in pull-up and...

Details Circuits for reducing leakage currents in pull-up and... Circuits for reducing leakage currents in pull-up and...

2005-02-22

2005-02-22

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S327000

Reexamination Certificate

active

06859083

ABSTRACT:
A pull-down circuit for pulling a high-impedance node to ground when a pull-down (PD) signal driving the pull-down circuit is Logic 1. The pull-down circuit comprises: 1) a first pull-down N-channel transistor having a drain coupled to the high-impedance node, a gate coupled to the PD signal, and a source coupled to a common node; 2) a second pull-down N-channel transistor having a drain coupled to the common node, a gate coupled to the PD signal, and a source coupled to a ground rail;, wherein the first and second pull-down N-channel transistors are off when the PD signal is Logic 0 and are on when the PD signal is Logic 1; and 3) a gate-biasing circuit driven by the PD signal. The gate-biasing circuit is off when the PD signal is Logic 1 and the gate-biasing circuit applies a Logic 1 bias voltage to the common node when the PD signal is Logic 0. The Logic 1 bias voltage creates a negative Vgs bias on the first pull-down N-channel transistor when the PD signal is Logic 0. An analogous pull-up circuit also is disclosed.

REFERENCES:
patent: 4956691 (1990-09-01), Culley et al.
patent: 5726588 (1998-03-01), Fiedler
patent: 5748025 (1998-05-01), Ng et al.
patent: 5834948 (1998-11-01), Yoshizaki et al.
patent: 6211704 (2001-04-01), Kong
patent: 6262593 (2001-07-01), Sobelman et al.
patent: 6538466 (2003-03-01), Lovett

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