Circuits for locally generating non-integral divided clocks...

Details Circuits for locally generating non-integral divided clocks... Circuits for locally generating non-integral divided clocks...

2008-01-15

2008-01-15

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S291000

Reexamination Certificate

active

07319348

ABSTRACT:
Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates a control signal in response to the counter. Staging latches receive the control signal and generate a clock high signal and a clock low signal, the clock high signal and the clock low signal having patterns derived from a waveform of a target divided ratio clock, the clock high signal and the clock low signals have patterns that match the targeted divided clock frequency and duty cycle. A local pass gate receives the clock low signal and the clock high signal and generates an (n+0.5)-to-1 clock signal in response to the global clock signal, the clock high signal and the clock low signal.

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Japanese Patent, “Patent Abstracts of Japan”, (C) 1994, JPO & Japio.

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