Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific current responsive fault sensor
Reexamination Certificate
2000-08-04
2003-03-04
Tso, Edward H. (Department: 2838)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific current responsive fault sensor
Reexamination Certificate
active
06529359
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to circuits for the protection of a MOS output drive from electrical overstress (EOS) or electrostatic discharge (ES) stress, and, more particularly, to circuits for the dynamic turn off of an NMOS output driver during EOS/ESD stress.
BACKGROUND OF THE INVENTION
An NMOS output driver is subject to being damaged when subjected to EOS/ESD stress. Heretofore, for EOS/ESD protection of an I/O pad, either the NMOS output drivers was designed to be self-protecting, or an electrical EOS/ESD clamp was added in parallel to the NMOS output driver. For various reasons the use of an electrical EOS/ESD clamp is preferred for this purpose. However, when an electrical EOS/ESD clamp is added, a problem can arise when the EOS or ESD stress is applied to the I/O pad. There are several stress situations where as a result of the application of a transient over voltage stress at the I/O pad, the circuit or part of the circuit gets powered up dynamically. In such situations, the pre-drive circuits will force either a high or low state at the gate of the final output drivers which is undesirable.
SUMMARY OF THE INVENTION
A circuit for the protection of an output driver NMOS transistor during EOS/ESD stress includes an output driver NMOS transistor and an output driver PMOS transistor connected in series between a Vdd line and a Vss line with the gates of the output driver transistors being connected together. An I/O pad is connected to the junction between the output driver transistors. A pre-driver stage includes an NMOS transistor and a PMOS transistor connected in series between the Vss line and the Vdd line with the gates of the pre-driver transistors being connected together. The output of the pro driver stage is connected to the gates of the output driver transistors. A gate clamp has a first connection to the Vss line, a second connection to the junction between the pre-driver transistors, a third connection to the I/O pad and a fourth connection to the gate of the output driver NMOS transistor. An ESD clamp is connected between the I/O pad and the Vss line and has a connection to the third connection of the gate clamp.
REFERENCES:
patent: 5345357 (1994-09-01), Pianka
patent: 5508649 (1996-04-01), Shay
patent: 5561577 (1996-10-01), Motley
patent: 5617283 (1997-04-01), Krakauer et al.
patent: 5708549 (1998-01-01), Croft
patent: 5729419 (1998-03-01), Lien
patent: 5754381 (1998-05-01), Ker
patent: 5838146 (1998-11-01), Singer
patent: 5852541 (1998-12-01), Lin et al.
patent: 5901022 (1999-05-01), Ker
patent: 5917689 (1999-06-01), English et al.
patent: 6028450 (2000-02-01), Nance
patent: 6091594 (2000-07-01), Williamson et al.
patent: 6157530 (2000-12-01), Pequignot et al.
patent: 0 575 062 (1993-12-01), None
patent: 2 305 035 (1997-03-01), None
Avery Leslie Ronald
Verhaege Koen Gerard Maria
Burke W.
Sarnoff Corporation
Tibbits Pia
Tso Edward H.
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