Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2002-02-27
2003-12-02
Lam, Tuan T (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S293000, C327S295000, C327S333000
Reexamination Certificate
active
06657474
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system in which a low voltage swing differential global clock network is applied on an integrated circuit chip.
BACKGROUND
In integrated circuits, inverters may be used to drive clock signals from a generation point where the signals are generated to the various points on an integrated circuit chip. The inverters are distributed throughout the integrated circuit chip, and function as inverting amplifiers which amplify the signals to compensate for any loss of signal occurred during propagation from the generation point at a central location to the various points on the chip.
FIG. 1
shows one exemplary embodiment of a full voltage swing clocking network, where the signals are driven from a generation point at a central location to receiving points at the four corners of an integrated circuit chip. As shown in
FIG. 1
, signals generated at the central location are driven to the corners, or local ends, through a network. This network, or clock tree
10
, radiates from the phase locked loop (PLL) to the local ends, and includes a plurality of inverters
101
. Each inverter
101
provides full voltage swing signals from ground to the supply voltage.
REFERENCES:
patent: 5774007 (1998-06-01), Soneda
patent: 6323714 (2001-11-01), Naffziger et al.
patent: 6433606 (2002-08-01), Arai
patent: 6466074 (2002-10-01), Vakil et al.
Varadarajan, Hemmige; Kumar, Sudarshan; Reitsma, Mike; Madhyastha, Sadhana; Design Comparison: Differential and Single-ended Clock Networks; Intel Design and Test Technology Conference; p. 1-5; 2000.
Varadarajan; Advanced Circuit Design; Food for Thought on Lowering Power and/or Raising uP Performance; Chapter 8; p. 81-8-10, Sep. 19, 2000.
Intel Corporation
Lam Tuan T
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