Circuits and methods to minimize thermally generated offset...

Details Circuits and methods to minimize thermally generated offset... Circuits and methods to minimize thermally generated offset...

2011-05-24

2011-05-24

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

External effect

Temperature

C330S256000

Reexamination Certificate

active

07948297

ABSTRACT:
A circuit to minimize thermally generated offset voltages includes a differential pair of transistors having a first transistor and a second transistor and coupled to a current source, a differential input having a first input coupled to the first transistor and having a second input coupled to the second transistor, a pair of bypass transistors having a first bypass transistor and a second bypass transistor, the first bypass transistor coupled in parallel with the first transistor and the second bypass transistor coupled in parallel with the second transistor, wherein the pair of bypass transistors is coupled to the current source, and control circuitry coupled to the pair of bypass transistors for controlling current through the pair of bypass transistors.

REFERENCES:
patent: 4724337 (1988-02-01), Maeda et al.
patent: 5610547 (1997-03-01), Koyama et al.
patent: 7012343 (2006-03-01), Inn et al.

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