Circuits and methods for selectively coupling redundant elements

Details Circuits and methods for selectively coupling redundant elements Circuits and methods for selectively coupling redundant elements

1998-02-27

2000-06-20

Nelms, David

Harvesters

365200, G11C 800

Patent

active

060772115

ABSTRACT:
A circuit and method for selectively coupling redundant components into an integrated circuit. Global I/O lines are coupled to local I/O lines through a number of multiplexors. Bitlines are grouped into blocks of bitlines. A fuse bank couples to the number of multiplexors through a logic/select circuit. When at least one fuse's state indicates that the associated I/O line is inoperable, the logic/select circuit switches the coupling to connect the global I/O line with a redundant local I/O line. The redundant local I/O's are configured to access the original block of bitlines. The arrangement conserves precious chip space and preserves uniform timing between normal and redundant data.

REFERENCES:
patent: 5281868 (1994-01-01), Morgan
patent: 5574689 (1996-11-01), Morgan
patent: 5583463 (1996-12-01), Merritt
patent: 5627786 (1997-05-01), Roohparvar
patent: 5706292 (1998-01-01), Merritt
patent: 5812466 (1998-09-01), Lee et al.

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