Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2002-01-18
2003-07-01
Le, N. (Department: 2858)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S155000, C341S120000
Reexamination Certificate
active
06587066
ABSTRACT:
FIELD OF INVENTION
The present invention relates in general to switched-capacitor circuits and methods and in particular to circuits and methods for sampling an input signal in a charge redistribution based analog to digital converter.
BACKGROUND OF INVENTION
One particular technique for performing analog to digital (A/D) conversion is through successive approximation. The basic successive approximation A/D converter (ADC) includes an analog comparator and a clocked feedback loop having a successive approximation register (SAR) and a digital to analog converter (DAC).
Generally, the analog input signal voltage is sampled onto an array of weighted capacitors during the sampling phase, the top plates of which are coupled to one comparator input. The other comparator input is coupled to a comparison voltage, which could be a fixed reference voltage in a single-ended system or the voltage at the top plates of second capacitor array in a differential system.
During the first clock cycle of the subsequent conversion phase, the bottom plate of the capacitor representing the digital most significant bit (MSB) is coupled to a reference voltage while the bottom plates of the remaining capacitors in the array are coupled to ground or a second reference voltage (ground will be assumed here). The new top plate voltage appears at the input of the comparator and is compared against the comparison voltage. If the new top plate voltage is below the comparison voltage, then the MSB is “kept” by the SAR in the feedback loop by maintaining its bottom plate coupled to the reference voltage. On the other hand, if the top plate voltage is above the comparison voltage, the SAR couples and the bottom plate of the MSB capacitor to ground. The bottom plate of the second MSB is then coupled to the reference voltage and the same test is performed to determine the state of the next digital code bit. The successive approximation algorithm continues by repeating this procedure for the remaining capacitors in the array such that the voltage difference at the inputs to the comparator converges to zero. At the end of this bit cycling process, the configuration of the switches coupling the bottom plates either to Vref or Gnd represents the input sample in digital form.
Successive approximation A/D converters are useful a wide range of applications, including data acquisition, test equipment, instrumentation, cellular communications, among others. Notwithstanding, in order to improve and broaden the utility of this type of A/D converter, significant challenges remain to be addressed. These challenges include improving the device speed given a set of process constraints, reducing the coding error rate, handling metastable states and calibration of the DAC.
SUMMARY OF INVENTION
In switched-capacitor charge redistribution analog to digital converters, a small track switch on-resistance is desirable to achieve a large sampling bandwidth. According to the inventive principles, these track switches operate from an increased common mode voltage which in turn maximizes the turn-on voltage across the track switches thereby lowering their on-resistance. A trade-off is then made by inserting additional cycles during the comparison phase of the charge redistribution process to insure that the top plates voltage of the sampling capacitors does not go above the supply voltage or below ground to preserve charge.
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Cirrus Logic Inc.
Hamdan Wasseem H.
Le N.
Murphy, Esq. James J.
Winstead Sechrest & Minick P.C.
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