Circuits and methods for read-enabling memory devices synchronou

Details Circuits and methods for read-enabling memory devices synchronou Circuits and methods for read-enabling memory devices synchronou

1997-04-24

1999-03-02

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

058780491

ABSTRACT:
A circuit for read-enabling a memory device with checking of the minimum functionality conditions of the memory cells and reading circuits, particularly for non-volatile memories, having a structure for reproducing the operating conditions within the memory matrix to determine the minimum duration of the step for pre-charging the bit lines involved in the reading operation, the structure being adapted to generate a pre-charge step interruption signal that depends on the reaching of the minimum functionality conditions; a mechanism for generating a power-on-reset signal for enabling reading when the minimum functionality conditions for reading correctness are reached, the power-on-reset signal generating mechanism being adapted to drive a control logic mechanism as well as a reading control and stimulation mechanism. The circuit further includes a memory mechanism for the pre-charge step, which is driven by the structure for reproducing the operating conditions within the memory matrix, by the control logic mechanism, and by the reading control and stimulation mechanism, the memory mechanism for the pre-charge step causing, at the onset of the minimum functionality conditions, the end of the pre-charge step to perform a first reading of the memory cells in assured conditions.

REFERENCES:
patent: 5430882 (1995-07-01), Tilghman et al.

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