Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synthesizer
Reexamination Certificate
2001-06-27
2003-02-11
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synthesizer
C327S119000, C327S129000, C708S275000, C331S057000
Reexamination Certificate
active
06518802
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to numerically controlled oscillators. More specifically, the invention relates to a numerically controlled oscillator for accurately outputting digital representations of sinusoidal waves.
2. Background and Related Art
Numerically controlled oscillators (NCOs) are used to output digital representations of sinusoidal waves at a specified output frequency. Typically, an NCO receives a digital input called a “frequency word” from which the desired output frequency may be determined. Historically, the maximum output frequency of NCOs has been limited to half of the sampling frequency. For example, a conventional NCO with a system clock (which is used as a measure of the maximum sampling rate) operating at 130 MHz could not accurately generate a sinusoidal wave having a frequency greater than 65 MHz.
FIG. 1
illustrates the structure of a conventional NCO that generates a digital representation of a sinusoidal wave. As shown in
FIG. 1
, sample phase generator
100
includes delay
101
, summer
102
, and bit select
103
. Sample phase generator
100
receives system clock
105
and frequency word
106
as inputs. System clock
105
operates at a certain frequency, which is the maximum sampling frequency of the NCO. Frequency word
106
is a configurable parameter used to specify the desired output frequency.
In operation, summer
102
receives frequency word
106
and the previous value from delay
101
as inputs. Each time system clock
105
clocks, the output from summer
102
is input into bit select
103
and back into delay
101
. Bit select
103
outputs the 8 most significant bits of the signal output from summer
102
.
If coupled to a conventional digital-to-analog converter (DAC), the output from bit select
103
, as plotted with time, would be a stepped saw tooth waveform with a frequency equal to the selected output frequency. An example of this is saw tooth waveform
107
. However, a saw tooth waveform is typically not useful, and most NCOs include circuitry, such as conversion circuitry
104
, that converts saw tooth waveform data into data that may be used to generate a more useful repeated waveform. The value output from the sample phase generator
100
represents the phase value of the more useful repeated waveform. The conversion circuitry
104
then generates the value of the repeated waveform at that phase value. Such conversion circuitry may convert saw tooth waveform data into digital sinusoidal waveform data (represented generally by sinusoidal waveform
108
), which represents the output of the NCO. When the output of the conversion circuitry
104
is sent to a DAC, the DAC will output a stepwise approximation of a sinusoidal wave at the desired output frequency.
Conversion circuitry
104
may be, for example, a sine/cosine lookup table. In this instance, conversion circuitry
104
would include a series of entries that correspond to samples of a sinusoidal wave. In
FIG. 1
, the eight-bit output from sample phase generator
100
may have 256 (i.e., 2
8
) possible phase values. Accordingly, the lookup table would have 256 possible output values corresponding to the 256 possible input values. Limiting the lookup table to 256 possible output values decreases the size of the NCO as compared to NCOs that have lookup tables of more refined resolution. For example, if all 17 bits of the output from summer
102
were provided to the conversion circuitry
104
, the conversion circuitry need to handle 2
17
(i.e., 131,072) different input permutations using 131,072 different entries. This kind of lookup table would typically be too large to be practical.
The output repeated waveform has a frequency spectrum with a strong line at the desired output frequency, but also includes lines that are separated from multiples of the clock frequency by plus or minus the desired output frequency. For example, if an NCO with a system clock of 130 MHz were used to generate a sinusoidal wave at 15 MHz, the output would also include a strong frequency component at 15 MHz. However, there would also be frequency components at 145 MHz (i.e., 130 MHz plus 15 MHz) and 115 MHz (i.e., 130 MHz minus 15 MHz) and smaller frequency components at 275 MHz (i.e., 2 times 130 MHz plus 15 MHz) and 245 MHz (i.e., 2 times 130 MHz minus 15 MHz), and so forth. Typically, such spurious frequency components may be removed using a low pass filter with a sharp cutoff below half of the clock frequency.
As the desired output frequency rises, the unwanted frequency that occurs at the clock frequency minus the desired output frequency draws closer to the desired output frequency. For example, if the clock frequency was 130 MHz and the desired output frequency was 60 MHz, there would be a spurious frequency component at 70 MHz (i.e., 130 MHz minus 60 MHz). The desired output frequency and the lowest spurious frequency component meet when the desired output frequency equals half of the clock frequency. In the example of an NCO with a system clock of 130 MHz, this would occur when the desired output frequency was 65 MHz. When this occurs, even a low pass filter with a very sharp cutoff cannot be used to remove spurious frequency components, because such a filter would remove desired frequency components as well. Thus, a digital representation of a sinusoidal wave at half the clock frequency or greater will not be sufficiently accurate.
Current technology limits clock rates on NCOs to around 200 MHz. This limits the output frequency of accurately generated sinusoidal waves to around 100 MHz. However, in many instances, it would be of benefit to accurately generate a digital representation of a sinusoidal wave with an output frequency higher than 100 MHz. In the case of NCOs, which do not employ the latest technology, and thus have slower clock rates, it would also be of benefit to accurately generate digital representations of sinusoidal waves at greater than one half the frequency of the clock frequency. For example, one might want to generate a 100 MHz sinusoidal wave using an NCO with a system clock of 130 MHz.
Therefore, what are desired are systems and methods for accurately generating a digital representation of a sinusoidal wave at greater than half the frequency of the sampling or clock frequency.
SUMMARY OF THE INVENTION
In accordance with the present invention, an NCO receives data representing digital samples of a sinusoidal wave at the desired output frequency. When a digital representation of a sinusoidal wave is to be generated at a desired output frequency that is near to or greater than one half the sampling rate, the samples are calculated over multiple cycles of the sinusoidal wave. The calculated samples are then stored in a circular shift register. The number of samples to be taken and the number of cycles over which the samples are accumulated are calculated using the sampling rate (system clock frequency) and the desired output frequency.
First, a greatest common factor of the sampling rate and specified frequency is calculated. For instance, if the sampling rate was 130 MHz and the specified frequency was 100 MHz, the greatest common factor would be 10. The number of samples that are to be buffered is calculated by dividing the sampling rate by the greatest common factor. In the given example, if the sampling rate was 130 MHz and the greatest common factor was 10, the number of samples would be thirteen. Also, the number of cycles over which the samples will be accumulated is calculated by dividing the desired output frequency by the greatest common factor. Returning to the example, if the desired output frequency is 100 MHz and the greatest common factor is 10, it will take ten cycles for the thirteen samples to be accumulated.
In the example, thirteen samples will be calculated over a period of ten cycles and the thirteen samples will be stored in a circular shift register. In the example, since ten is a whole number, the value of samples from subsequent groups of ten cycles would be identical to those
Coffin III Louis F.
Tu Dan Q.
Callahan Timothy P.
Nguyen Minh
Webtv Networks, Inc.
Workman & Nydegger & Seeley
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