Circuits and methods for extracting a clock from a biphase...

Details Circuits and methods for extracting a clock from a biphase... Circuits and methods for extracting a clock from a biphase...

2000-12-05

2004-08-24

Woo, Stella (Department: 2644)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Digital audio data processing system

C375S333000, C375S361000

Reexamination Certificate

active

06782300

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to electronic data links and in particular, to methods and circuits for extracting a clock from a biphase encoded bit stream and systems using the same.
2. Description of the Related Art
Biphase encoding has the significant advantage of allowing data, control signals, and embedded clocks to be transferred serially across a single conductor. Generally, data is generated by the transmitter by selectively using the active and inactive edges of a Bit Clock. For example, in the most common encoding scheme, data bits of logic value 0 are represented by making logic level transitions only on the active bit clock edges and data bits of logic value 1 are represented by making logic level transitions on both the active and inactive bit clock edges. At the receiver, both the data and the embedded clocks, including the Bit Clock and the Frame Clock, are extracted.
One particular application of biphase encoding is in the transmission of digital audio data between various systems and devices. The AES/EBU (Audio Engineering Society/European Broadcasting Union) interface is one application which supports the encoding, transmission and decoding of two channels of digital audio data, along with control information and error correction bits. In this Professional Status Block format, data can be transferred via a coaxial transmission line or a twisted shielded pair. The S/PDIF (Sony—Phillips Digital Interface) is the consumer variant of the AES/EBU standard, and supports data transmission via either a coaxial or an optical physical layer. In both cases, only a single conductor is required between the transmitting and receiving devices, as mentioned above.
Current techniques for extracting the embedded clocks from a biphase encoded data stream rely on a phase locked loop (PLL), along with prior knowledge of the frequency of the Frame Clock. Generally, the PLL is set up with the appropriate operating conditions to generate clock signal of a selected multiple of the Frame Clock. This clock signal is then used to decode the bitstream. Among other things, these techniques require additional hardware and require the prior knowledge of the Frame Clock frequency.
Consequently, the need has arisen for improved techniques for extracting embedded clocks from a bitstream, such as a biphase encoded bitstream. The amount of hardware required should be minimized and prior knowledge of the Frame Clock frequency should not be required. Moreover, jitter in the Frame Clock should also be minimized. These techniques should be applicable to a wide range of circuits and systems operating on biphase encoded, including, but not limited to, those processing AES/EBU and S/PDIF data.
SUMMARY OF THE INVENTION
According to one embodiment of the principles of the present invention a method is disclosed for generating a frame clock from a biphase encoded bit audio stream. A sequence of bit phase transitions in the audio bit stream is detected, each pair of consecutive bit phase transitions defining a sample having a sample size. During a preamble detection phase, a sample length is determined for each of the sequence of samples by determining a number of predetermined least common multiples in the corresponding sample size and then decoding the sample lengths for the sequence of samples to identify a preamble of a given preamble type. During a data detection phase, the sample lengths for a sequence of data bits are determined from the biphase bit stream and the sample lengths of the sequence of data bits decoded into binary data bits. The frame clock is generated by determining an expected value of the frame clock level and performing an XNOR operation using the expected value of the frame clock level and the bit phase data to generate an intermediate signal. During a time window, the intermediate signal is registered with an oversampling clock and the registered intermediate signal and the biphase date used in the XOR operation during the time window to generate the clock edge of the frame clock.
The principles of the present invention have a number of advantages over prior art clock extraction schemes. Among other things, no prior information about the clock being extracted is required. Moreover, these principles can be applied to clocks of many different frequencies. While not limited thereto, the disclosed principles and circuits can advantageously be applied to the extraction of clocks from AES/EBU and S/PDIF bit streams.


REFERENCES:
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patent: 6249555 (2001-06-01), Rainbolt
patent: 6567487 (2003-05-01), Pilz
patent: 36 32 719 (1988-03-01), None
patent: 0 453 063 (1991-10-01), None
patent: 0 930 713 (1999-07-01), None
patent: WO 98 16040 (1998-04-01), None

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