Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
1999-08-26
2001-01-23
Han, Jessica (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S288000
Reexamination Certificate
active
06177787
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to switching regulator circuits. More particularly, the present invention relates to circuits and methods for controlling timing and slope compensation in switching regulator circuits.
The purpose of a voltage regulator is to provide a predetermined and substantially constant output voltage to a load from a voltage source which may be poorly-specified or fluctuating. In a typical linear voltage regulator, the voltage at the regulator output is regulated by controlling the flow of current passing through a pass element (such as a power transistor) from the voltage source to the load.
In typical switching voltage regulators, however, the flow of current from the voltage source to the load is not steady, but rather is in discrete current pulses. To convert these discrete current pulses into a steady load current, typical switching regulators employ an inductive energy storage element. To create the discrete current pulses, typical switching regulators also employ a switch (such as a power transistor) that is coupled either in series or parallel with the load. By controlling the duty cycle of this switch (i.e., the percentage of time that the switch is ON relative to the total period of the switching cycle), the switching voltage regulator can regulate the voltage at the load. In a current-mode switching voltage regulator (i.e., a switching regulator that is controlled by a current signal in the regulator), the regulator can become unstable when the duty cycle exceeds 50% (i.e., when the switch is ON for more than 50% of a given switching period). Stability is often maintained in such current-mode switching voltage regulators by adjusting the current signal used to control the regulator with a slope compensation signal.
One method of producing the slope compensation signal is to use a portion of an oscillator signal as the compensation signal. Such an oscillator signal may be, for example, a sawtooth waveform that is also used to generate a clock signal used to control the switching of the regulator. Using a portion of an oscillator signal as the slope compensation signal may be ineffective, however, when the oscillator signal does not have the desired waveform or is out of phase with the desired slope compensation signal. For example, when the oscillator signal is a square wave, using the oscillator signal as the slope compensation signal may be ineffective because it may be undesirable to have a drastic change in the slope compensation signal on the leading edge of the oscillator signal and to have only a two-level slope compensation signal. As another example, when the oscillator signal is a sawtooth waveform, using the oscillator signal as the slope compensation signal may be ineffective because it may be undesirable to have a linear increase in the slope compensation signal. As still another example, with any type of oscillator waveform, using the oscillator signal as the slope compensation signal may be ineffective because the switching of the regulator may be out of phase with the oscillator signal, and therefore, the desired slope compensation signal may also be out of phase with the oscillator signal.
In some switching regulators, it is common to connect to a single input power source multiple switching output stages that are synchronized to a common clock signal and that each produce a different output voltage. Similarly, output stages of multiple switching regulators are also commonly connected in parallel to a single input power source and synchronously operated based on a common clock signal. However, when each of the switches in these output stages turn ON simultaneously because they are connected to a single clock signal, excessive ripple currents may be induced in the input and output currents of the output stages. For example, the peak input ripple current is roughly equal to the combined sum of all of the peak inductor currents. As this input ripple current increases, power loss increases dramatically since the root-mean-squared (RMS) power lost in the equivalent source resistance (ESR) of the input capacitance is proportional to the square of the input current. Consequently, low equivalent series resistance input and output capacitances must frequently be provided in these output stages and switching regulators to minimize the loss due to these ripple currents.
In view of the foregoing, it would be desirable to provide switching regulator circuits that produce a slope compensation signal having a waveform that need not match the waveform of any oscillator signal.
It would also be desirable to provide switching regulator circuits that produce a slope compensation signal having a period that need not be the same as the oscillator period.
It would further be desirable to provide switching regulator circuits that reduce input and output ripple currents from the magnitudes induced by simultaneous switching of multiple output stages.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide switching regulator circuits that produce a slope compensation signal having a waveform that need not match the waveform of any oscillator signal.
It is also an object of the present invention to provide switching regulator circuits that produce a slope compensation signal having a period that need not be the same as the oscillator period.
It is a further object of the present invention to provide switching regulator circuits that prevent excessive input and output ripple currents from being induced by simultaneous switching of multiple output stages.
In accordance with these and other objects of the invention, there are provided switching regulator circuits and methods that include a timing control circuit that controls the timing of the switching of one or more switching regulator output stages so that the switching occurs at evenly spaced time intervals, and a slope compensation circuit that produces a slope compensation signal having a waveform that may be different than the waveform of any oscillator signal, or that may have a different period than the oscillator signal.
Timing control is provided in the switching regulators of the present invention by generating evenly spaced clock phase signals that are used to control the switching of multiple switching regulator output stages. These clock phase signals are produced by dividing a master clock signal in half using a T flip-flop (to insure that the resultant signal has a 50% duty cycle), and then further dividing the resultant signal using a “rolling clock” (or “Johnson counter”) formed from D flip-flops. When formed from N D flip-flops, the rolling clock provides 2N clock phase signals and runs at 1/(4N) of the master clock frequency. For example, with three D flip-flops, the rolling clock provides 6 clock phase signals and runs at {fraction (1/12)} of the master clock frequency. Any of the clock phase signals provided by the rolling counter may be further decoded using another D flip-flop and an inverter to produce an output signal that is in quadrature phase with the decoded clock phase signal (i.e., lags one master clock signal period behind the decoded clock phase signal).
By dividing and decoding the master clock signal in this way, switching regulator timing control circuits can use master clock oscillators that operate at a much higher frequency than that at which the switching regulator is operating. Two advantages of using such higher-frequency oscillators are that they are typically smaller and less expensive than lower-frequency oscillators.
Using these phase signals, the switching times of multiple switching regulator output stages can be evenly spaced out over the course of a single regulator switching period so that RMS input current and induced ripple current (due to the effective increase in switching regulator frequency and non-overlap) are minimized. For example, with three output stages, phases one, three, and five can be used to space the output stages' switch-on times 120 degrees apart in the regulator switching
Byrne Matthew T.
Fish & Neave
Han Jessica
Linear Technology Corporation
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