Circuits and methods for clock signal duty-cycle correction

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control

Reexamination Certificate

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C327S172000

Reexamination Certificate

active

07999589

ABSTRACT:
Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.

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patent: 6927642 (2005-08-01), Hsieh
patent: 7078949 (2006-07-01), Kim et al.
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patent: 7701273 (2010-04-01), Choi
patent: 7791388 (2010-09-01), Gomm
patent: 2007/0159224 (2007-07-01), Dwarka et al.

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