Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2003-10-28
2004-09-21
Jeanglaude, Jean Bruner (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S061000, C341S155000
Reexamination Certificate
active
06795007
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to delta-sigma analog-to-digital converters. More specifically, the present invention provides circuits and methods for a delta-sigma analog-to-digital converter having a variable oversample ratio produce a constant fullscale output with reduced circuit complexity, die area, and power dissipation.
BACKGROUND OF THE INVENTION
Analog-to-digital converters (“ADC”) are electronic devices that convert analog signals into digital representations. As such, they form an integral part of any digital system requiring an interface between external analog signals and the digital circuits in the system.
A block diagram of an ADC is shown in FIG.
1
. ADC
20
uses reference voltage V
ref
to convert analog signal V
in
into N-bit digital signal D
out
. Analog signal V
in
is first sampled into a discrete-time signal and then the discrete-time signal is quantized into a finite number of quantization levels to produce D
out
. For an N-bit D
out
, V
in
is quantized into 2
N
levels, with each level separated by a quantization step size. As a result of the quantization, a number of input voltage signal levels produces identical digital outputs.
Reference voltage V
ref
provides the range of conversion for the ADC so that input signal V
in
may range from 0 to +V
ref
or from −V
ref
to +V
ref
(for a bipolar ADC). If V
in
is equal to or larger than V
ref
, commonly referred to as the fullscale input, D
out
outputs all ones and is referred to as the fullscale output. If V
in
is equal to or smaller than 0/−V
ref
V, D
out
outputs all zeros. For V
in
between these two voltage levels, D
out
is a binary number corresponding to the V
in
signal level such that a change in V
in
of a quantization step size of V
ref
/2
N
corresponds to a 1-bit change in the least significant bit (“LSB”) of D
out
.
The performance of an ADC is evaluated based on its resolution, accuracy, and speed. The resolution of an ADC is determined by the number of bits used to represent D
out
. An N-bit ADC has a resolution of 1:2
N
. The accuracy of the conversion is represented in terms of the quantization step size/bit or in terms of the RMS noise generated for a fixed input. The speed or conversion rate of the ADC is the time it takes for the ADC to perform a conversion. The higher the number of times an input is sampled per conversion result, the higher the resolution and accuracy of the conversion and the slower the speed of the ADC. For example, an 8-bit ADC having a V
ref
of 5 V quantizes the input voltage into 256 levels with a quantization step size of 19.5 mV. That is, the ADC cannot resolve input voltage differences smaller than 19.5 mV, i.e., this 8-bit ADC has an accuracy of 19.5 mV/bit. In contrast, a 12-bit ADC with 4096 quantization levels can resolve voltage differences as small as 1.2 mV, i.e., its accuracy is 1.2 mV/bit.
The trade-off between resolution, accuracy, and speed of an ADC is highly dependent on its architecture. There are many different architectures of ADCs available, with the most popular ones being the parallel or flash converter, the successive approximation ADC, the voltage-to-frequency ADC, the integrating ADC, and the delta-sigma or sigma-delta ADC. The parallel converter is the simplest and fastest ADC, with the N output bits determined in parallel by 2
N
-1 comparators. However, because this architecture requires a large number of comparators, commercial parallel ADCs have very limited resolution, up to 1:1024 (10-bit outputs). Examples of commercially available parallel ADCs include the 8-bit ADC0820, sold by National Semiconductor, of Santa Clara, Calif., and the 8-bit AD7820, sold by Analog Devices, Inc., of Northwood, Mass.
Successive approximation ADCs are also relatively fast, employing a digital-to-analog converter (“DAC”) to try out various digital output levels and a single comparator to compare the result of the DAC conversion to the analog input voltage. For a N-bit successive approximation ADC, N comparisons are required. Successive approximation ADCs are inexpensive to implement and commercial implementations typically range from 8 to 16 bits. Examples of commercially available successive approximation ADCs include the 12-bit LTC1410, sold by Linear Technology Corp., of Milpitas, Calif., and the 8-bit ADC0801, sold by National Semiconductor, of Santa Clara, Calif.
If speed is not important, voltage-to-frequency ADCs offer an inexpensive architecture suitable for converting slow and often noisy signals. These ADCs convert an input voltage into an output pulse train whose frequency is proportional to the input voltage. The output frequency is determined by counting pulses over a fixed time interval. Commercially available voltage-to-frequency ADCs have outputs ranging from 8 to 12 bits and are useful for applications in noisy environments when an output frequency is desired, such as in remote sensing applications when an analog input voltage is converted to an output pulse train at a remote location and the output pulse train is transmitted over a long distance to eliminate the noise introduced in the transmission of an analog signal. Examples of voltage-to-frequency ADCs include the AD650, sold by Analog Devices, Inc., of Northwood, Mass., and the LM331, sold by National Semiconductor, of Santa Clara, Calif.
For low speed applications requiring higher resolution, integrating ADCs provide a better alternative to voltage-to-frequency ADCs. Integrating ADCs measure the charge and discharge times of a capacitor to determine the digital output according to the relationship between the input voltage and the capacitor charge and discharge times. In single-slope integrating ADCs, the relationship is determined by counting clock pulses until a comparator finds the capacitor charged to the input voltage. The digital output is given by the number of clock pulses. In dual-slope integrating ADCs, the relationship is determined by charging the capacitor for a fixed time period with a current that is proportional to the input voltage and subsequently discharging the capacitor with a constant current. The time to discharge the capacitor is proportional to the input voltage and the digital output is given by the number of clock pulses counted while the capacitor is discharging. Single-slope integrating ADCs are simple to implement but not as accurate as dual-slope integrating ADCs, which are commonly used in high precision digital systems. The resolution of commercially available integrating ADCs may range from 1:2
10
to 1:2
20
. Examples include the 18-bit ALD500, sold by Advanced Linear Devices, Inc., of Sunnyvale, Calif., and the 18-bit AD1170, sold by Analog Devices, Inc., of Northwood, Mass.
Although the ADC architectures discussed above provide a wide range of choices in terms of resolution, accuracy, and speed, their analog components make it difficult to integrate their circuitry in high-speed VLSI technology. Because they operate at a relatively low sampling frequency, usually at the Nyquist rate of the input signal, they often require an external anti-aliasing analog filter and sample-and-hold circuitry to limit the frequency of the input signal. Additionally, these ADC architectures are vulnerable to noise and interference and require high-accuracy analog components in order to achieve high resolution.
Currently available delta-sigma ADCs provide a solution to the VLSI integration and noise problems of the previous ADC architectures. Delta-sigma ADCs use a low resolution (e.g., 1-bit) delta-sigma analog modulator running at very high sampling rates combined with a digital filter to achieve high output resolutions. The modulator oversamples the input signal, transforming it into a serial bit stream at a frequency well above the output rate. The digital filter then low-pass filters and decimates the bit stream generated by the modulator to achieve an improved resolution at a lower output rate. For example, a 20-bit delta-sigma ADC may be implemented by combining a 1-bit delta-sigma modulator sampli
Fish & Neave
Jeanglaude Jean Bruner
Linear Technology Corporation
Rowland Mark D.
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