Circuits and method for reducing voltage error when charging and

Details Circuits and method for reducing voltage error when charging and Circuits and method for reducing voltage error when charging and

1995-04-28

1996-08-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

327259, 327287, 327382, H03K 17687

Patent

active

055505031

ABSTRACT:
A circuit and method for reducing voltage error when charging and discharging a storage capacitor (44) through a transmission gate (43). The storage capacitor (44) stores or holds a voltage coupled through the transmission gate (43) when the transmission gate (43) is disabled. The circuit comprises a clock generation circuit (47) providing complementary clock signals for enabling and disabling the transmission gate (43) and a charge negating transmission gate (46). The clock generation circuit (47) provides the complementary clock signals simultaneously to the transmission gates (43, 46). Alternate paths for dissipating channel charge of the transistors which comprise the transmission gate (43) are not formed by providing the complementary clock signals simultaneously. The channel charge is then canceled by the charge negating transmission gate (46) reducing voltage error on the storage capacitor (44).

REFERENCES:
patent: 4508983 (1985-04-01), Allgood et al.
patent: 4511814 (1985-04-01), Matsuo et al.
patent: 4599522 (1986-07-01), Matsuo et al.
patent: 4628250 (1986-12-01), Lee
patent: 4929854 (1990-05-01), Iino et al.
patent: 4982116 (1991-01-01), Lee
patent: 5111072 (1992-05-01), Seidel
patent: 5306962 (1994-04-01), Lamb
patent: 5341031 (1994-08-01), Kinoshita et al.
patent: 5392205 (1995-02-01), Zavaleta
patent: 5440250 (1995-08-01), Albert
patent: 5453707 (1995-09-01), Hiratsuka et al.

Affiliated with

Also associated with

Rating

Circuits and method for reducing voltage error when charging and does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuits and method for reducing voltage error when charging and, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuits and method for reducing voltage error when charging and will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1058480