Circuits and apparatus which enable elimination of setup time an

Details Circuits and apparatus which enable elimination of setup time an Circuits and apparatus which enable elimination of setup time an

1985-07-05

1989-01-17

Eisenzopf, Reinhard J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307234, 324 73R, H03K 522, G01R 1512

Patent

active

047990236

ABSTRACT:
An improved digital testing device is presented which includes the capability to detect and avoid a pair of common sources of measurement error. One source of error occurs when measurements are made within a Setup time before a transition in the signal under test or during a Hold time after such a transition. This device includes the ability to detect when this occurs and to insert a relative delay between the measurements and transitions to eliminate such errors. The device also detects the existence of a 3-state condition of a point of the circuit under test during the period of a measurement and provides an output indication when such occurs.

REFERENCES:
patent: 4237423 (1980-12-01), Rhodes

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