Circuitry to reduce PLL lock acquisition time

Details Circuitry to reduce PLL lock acquisition time Circuitry to reduce PLL lock acquisition time

2005-09-06

2005-09-06

Nguyen, Linh My (Department: 2816)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331SDIG002

Reexamination Certificate

active

06940356

ABSTRACT:
A phase locked loop, PLL, is described with multiple parallel charge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.

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patent: 0 528 651 (1993-02-01), None
patent: WO 96/29785 (1996-09-01), None

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