Circuitry for transferring data from a data bus and temporary re

Details Circuitry for transferring data from a data bus and temporary re Circuitry for transferring data from a data bus and temporary re

1989-11-20

1993-06-22

Anderson, Lawrence E.

Boots, shoes, and leggings

395775, 364DIG1, 3642602, 3642719, G06F 1314

Patent

active

052222306

ABSTRACT:
A floating point processor (10) is provided having a multiplier (48) and an ALU (54) for performing arithmetic calculations simultaneously. The output of the multiplier (48) and ALU (54) are stored in a product register (64) and a sum register (66), respectively. Multiplexers (40,42,44,46) are provided at the inputs to the multiplier (48) and the ALU (54). The multiplexers choose between data in input registers (32,34), product and sum registers (64,66), and an output register (76). Since the multiplier (48) and ALU (54) operate simultaneously, and since the outputs of the multiplier (48) and ALU (54) are available to the multiplexers (40-46), product of sums calculations and sum of products calculations may be performed rapidly. An input stage (12) uses a temporary register (18) to store data from a data bus on the first clock edge, and configuration logic (28) for directing data from the data bus and the temporary register (18) to the input registers (32,34) on a second clock edge.

REFERENCES:
patent: 3820079 (1974-06-01), Bergh et al.
patent: 4016545 (1977-04-01), Lipovski
patent: 4370709 (1983-01-01), Fosdick
patent: 4398085 (1983-08-01), Benedict
"Microprocessors And Microcomputer Development Systems" by Rafiuzzaman, 1984, pp. 65-75, 150-153.

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